diff options
| author | Philippe Schenker <philippe.schenker@toradex.com> | 2020-11-23 19:04:41 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2020-11-29 00:12:17 +0000 |
| commit | 190e76e88d56831c9c8190ba06f015c2f3eb95cf (patch) | |
| tree | e4d9bb94fe04e455df3fd1a9aaa9014166f6b054 | |
| parent | c865e58fe9e1e2d01ff27f85723b119ce003c942 (diff) | |
ARM: dts: colibri-imx6ull: do not pull-up sd-clk but sd-cmd signal
From the SD-Card specification:
> The host shall supply power to the card so that the voltage is
> reached to V DD _min within 250ms and start to supply at least
> 74 SD clocks to the SD card with keeping CMD line to high. In case of
> SPI mode, CS shall be held to high during 74 clock cycles.
According to this information I think we should pull the CMD data
line like on other boards to 3.3V. Also on other boards we
do have the CLK signal pulled.
This looks like this got mixed that up.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
| -rw-r--r-- | arch/arm/boot/dts/imx6ull-colibri.dtsi | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 10d3605e0ac4..ad6a96b7f5b8 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -556,8 +556,8 @@ pinctrl_usdhc1: usdhc1-grp { fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 /* SODIMM 47 */ - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 /* SODIMM 190 */ + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */ + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */ @@ -567,8 +567,8 @@ pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 @@ -578,8 +578,8 @@ pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 @@ -594,7 +594,7 @@ MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10 >; |