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author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-05-27 13:32:18 +0800 |
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committer | Max Krummenacher <max.krummenacher@toradex.com> | 2020-11-26 13:51:58 +0000 |
commit | f08da8504c8b19e11f334cd637e3cb21d9a317b0 (patch) | |
tree | 8052cbafff0d6f2715d4adcf43d7bced22fa742c | |
parent | dcec956f9168c7f9a902cd44bd9a577f850de5cc (diff) |
MLK-24171-2 dt-binding: phy: update the clock modes of pcie phy
Update the clock modes of iMX8MP PCIe PHY in binding DOC.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit eade3750bf840948b29db26f0beabf10dea5f981)
-rw-r--r-- | Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt b/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt index 627b508ecadc..77841c4959b0 100644 --- a/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt +++ b/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt @@ -6,6 +6,8 @@ Required properties: - reg: The base address and length of the registers - clocks: Phandles to the clocks for each clock listed in clock-names - clock-names: Must contain "phy" +- ext_osc: Specify the reference clock source. 1: external oscilltor is + used as PCIe reference clock. 0: internal PLL is used. - power-domains: Phandle to the power domain that the device is part of Example: |