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authorPhilippe Schenker <philippe.schenker@toradex.com>2021-12-16 10:49:17 +0100
committerPhilippe Schenker <philippe.schenker@toradex.com>2021-12-17 11:08:30 +0100
commit4c1e53bd833b2f7a250751a0e0a94eb81d43a3ed (patch)
tree9310f26b2edb8118becca9ec50842ff617aa6267
parent3641f0fd8645402c0ba8d2ae88e7687a10ad9160 (diff)
arm64: dts: apalis-imx8: leave phy-reset in push-pull
In order to prevent backfeeding we have a sleep-state of our pins. Currently the phy-reset is put to open-drain input, High-Z and pull-down. This causes a pull-up on hardware and the configured pull-down to work against each other and causing some strange voltage level. Leave the phy-reset signal configured as push-pull and pull-up as the reset also needs to be high during runtime suspend. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
-rw-r--r--arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
index 72dcc4a4a6b2..2cba7b82de48 100644
--- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
@@ -1124,7 +1124,7 @@
IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040
IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040
IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040
- IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x04000040
+ IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020
IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 0x04000040
>;
};