summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMax Krummenacher <max.krummenacher@toradex.com>2021-02-13 18:33:58 +0100
committerMax Krummenacher <max.krummenacher@toradex.com>2021-02-17 17:44:31 +0100
commitd2feaf72c1aa06c8decf529b502083e67282a411 (patch)
tree58c387af9d45d5eb489ba62491f9ad64f7357770
parent31966f8362999b2c61ae158722f6b7673b6a8a60 (diff)
arm64: dts: imx8mm-verdin: define most properties for overlays
Define all non conflicting properties used in device tree overlays in disabled nodes and just set their status to okay in the overlay. This unifies with the way it is done for the Verdin iMX8M Plus. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
-rwxr-xr-xarch/arm64/boot/dts/freescale/imx8mm-verdin-v1.1.dtsi86
1 files changed, 86 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-v1.1.dtsi
index e63ca14f1964..0982d95357ea 100755
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-v1.1.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-v1.1.dtsi
@@ -17,6 +17,20 @@
rtc1 = &snvs_rtc;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 45 63 88 119 158 203 255>;
+ default-brightness-level = <4>;
+ /* Verdin MEZ_DSI_1_BKL_EN (SODIMM 21) */
+ enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mez_dsi_1_bkl_en>;
+ power-supply = <&reg_3p3v>;
+ /* Verdin MEZ_PWM_3_DSI (SODIMM 19) */
+ pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
+ status = "disabled";
+ };
+
/* fixed clock dedicated to SPI CAN controller */
clk20m: oscillator {
compatible = "fixed-clock";
@@ -529,6 +543,14 @@
};
};
+/* Verdin I2C_2_DSI */
+&i2c2 {
+ clock-frequency = <10000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "disabled";
+};
+
/* Verdin I2C_3_HDMI N/A */
/* Verdin I2C_4_CSI */
@@ -574,6 +596,43 @@
vcc-supply = <&reg_3p3v>;
};
+ lvds_ti_sn65dsi83: bridge@2c {
+ compatible = "ti,sn65dsi83";
+ /* Verdin MEZ_GPIO_1 (SODIMM 206) */
+ enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mez_gpio1>;
+ reg = <0x2c>;
+ status = "disabled";
+ ti,dsi-lanes = <4>;
+ ti,height-mm = <136>;
+ ti,lvds-bpp = <24>;
+ ti,lvds-format = <2>;
+ ti,width-mm = <217>;
+
+ display-timings {
+ native-mode = <&lvds_timing0>;
+
+ lvds_timing0: lt170410_2whc {
+ /*
+ * Take the minimum pixelclock as 71.1 MHz is
+ * not working on NXP i.MX8M Mini
+ */
+ clock-frequency = <68900000>;
+ hactive = <1280 1280 1280>;
+ hfront-porch = <23 60 71>;
+ hback-porch = <23 60 71>;
+ hsync-len = <15 40 47>;
+ vactive = <800 800 800>;
+ vfront-porch = <5 7 10>;
+ vback-porch = <5 7 10>;
+ vsync-len = <6 9 12>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+
/* Current measurement into module VCC */
hwmon: hwmon@40 {
compatible = "ti,ina219";
@@ -582,6 +641,33 @@
status = "disabled";
};
+ hdmi_lontium_lt8912: hdmi@48 {
+ compatible = "lontium,lt8912";
+ ddc-i2c-bus = <&i2c2>;
+ /* Verdin MEZ_DSI_1_INT HPD (SODIMM 17) shared with MEZ_GPIO_1 (SODIMM 206) */
+ hpd-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mez_dsi_1_int_hpd>, <&pinctrl_mez_gpio1>,
+ <&pinctrl_mez_gpio2>;
+ reg = <0x48>;
+ /* Verdin MEZ_GPIO_2 (SODIMM 208) */
+ reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+ };
+
+ atmel_mxt_ts: touch@4a {
+ compatible = "atmel,maxtouch";
+ /* Verdin MEZ_DSI_1_INT# (SODIMM 17) */
+ interrupt-parent = <&gpio3>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mez_dsi_1_int_n>, <&pinctrl_mez_gpio2>;
+ reg = <0x4a>;
+ /* Verdin MEZ_GPIO_2 (SODIMM 208) */
+ reset-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
/* EEPROM on display adapter (MIPI DSI Display Adapter) */
eeprom_display_adapter: eeprom@50 {
compatible = "st,24c02";