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| author | Philippe Schenker <philippe.schenker@toradex.com> | 2021-11-23 17:11:19 +0100 |
|---|---|---|
| committer | Philippe Schenker <philippe.schenker@toradex.com> | 2021-11-25 08:44:44 +0000 |
| commit | fee494b82862c4098d4b1232f0db55ee917055ad (patch) | |
| tree | 0e31d80fcc994ff71a0dc2f4871414cd92623521 | |
| parent | 42de66b9fbfcd7350834c903a98d686ef5a7a7df (diff) | |
ARM64: dts: verdin-imx8mm: dev-board: limit usdhc2 clock
Limit the USDHC2 clock to 100MHz as with certain SDIO cards the clock
frequency cannot go higher without being distorted.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi index 0313cf299418..4ffb60848db8 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi @@ -55,6 +55,11 @@ }; }; +/* Limit frequency on dev board due to long traces and bad signal integrity */ +&usdhc2 { + max-frequency = <100000000>; +}; + &wm8904_1a { status = "disabled"; }; |