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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2014-01-26 17:43:41 +0100
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2014-01-26 17:43:41 +0100
commit2939f05630869e46c664534cfd652f9560ba7a47 (patch)
tree1ed6d6b129a0f9f1ad1cd00397015bf31ec4c94e
parent0a6c0d28e0944151a2fa03529ca88b5b4612c2e8 (diff)
apalis_imx6: video dac oe polarity hack
The home-brew resistor video DAC on Apalis iMX6 uses DI0_PIN15 as output enable but with reversed polarity. 720p as well as 1080p also work albeit the later some 20 odd pixels shifted towards the top.
-rw-r--r--arch/arm/configs/apalis_imx6_defconfig2
-rw-r--r--drivers/video/mxc/mxc_ipuv3_fb.c8
2 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/configs/apalis_imx6_defconfig b/arch/arm/configs/apalis_imx6_defconfig
index 146447446173..559b0ac47dda 100644
--- a/arch/arm/configs/apalis_imx6_defconfig
+++ b/arch/arm/configs/apalis_imx6_defconfig
@@ -62,7 +62,7 @@ CONFIG_COMPACTION=y
CONFIG_KSM=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="ip=:::::eth0:on root=/dev/nfs rw netdevwait console=tty1 console=ttymxc0,115200n8 fbcon=map:1 fec_mac=00:14:2d:00:00:00"
+CONFIG_CMDLINE="ip=:::::eth0:on root=/dev/nfs rw netdevwait console=tty1 console=ttymxc0,115200n8 fbcon=map:1 fec_mac=00:14:2d:00:00:00 video=mxcfb0:dev=lcd,640x480M@60,if=RGB565 fbmem=10M"
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c
index 15db4c92925c..5f2b1bbedff7 100644
--- a/drivers/video/mxc/mxc_ipuv3_fb.c
+++ b/drivers/video/mxc/mxc_ipuv3_fb.c
@@ -589,7 +589,13 @@ static int mxcfb_set_par(struct fb_info *fbi)
sig_cfg.clk_pol = true;
if (fbi->var.sync & FB_SYNC_DATA_INVERT)
sig_cfg.data_pol = true;
- if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT))
+ if (
+/* Hack: The home-brew resistor video DAC on Apalis iMX6 uses DI0_PIN15 as
+ output enable but with reversed polarity. */
+#ifndef CONFIG_MACH_APALIS_IMX6
+ !
+#endif
+ (fbi->var.sync & FB_SYNC_OE_LOW_ACT))
sig_cfg.enable_pol = true;
if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
sig_cfg.clkidle_en = true;