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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2016-01-06 18:27:27 +0100
committerMax Krummenacher <max.krummenacher@toradex.com>2016-03-08 15:14:53 +0100
commit7893d2eab16af186d630cd3834a07b9a477385b4 (patch)
treed93e2bba410c27fb3db2fc6146f8cf50ebce4763
parent29a3e3db2da1cfa7579b94deacfc1ec5eb79355f (diff)
PCI: Apalis GEN1 forcing quirk
The Apalis evaluation board needs to set the link speed to 2.5 GT/s (GEN1). The default link speed setting is 5 GT/s (GEN2). 0x98 is the Link Control 2 PCIe Capability Register of the PEX8605 PCIe switch. The switch supports link speed auto negotiation, but falsely sets the link speed to 5 GT/s. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
-rw-r--r--drivers/pci/quirks.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 032460f2dc08..82077e4b5c72 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2140,6 +2140,21 @@ static void quirk_tile_plx_gen1(struct pci_dev *dev)
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
#endif /* CONFIG_TILEPRO */
+#ifdef CONFIG_PCI_FORCE_GEN1
+/*
+ * The Apalis evaluation board needs to set the link speed to 2.5 GT/s (GEN1).
+ * The default link speed setting is 5 GT/s (GEN2). 0x98 is the Link Control 2
+ * PCIe Capability Register of the PEX8605 PCIe switch. The switch supports
+ * link speed auto negotiation, but falsely sets the link speed to 5 GT/s.
+ */
+static void quirk_apalis_plx_gen1(struct pci_dev *dev)
+{
+ pci_write_config_dword(dev, 0x98, 0x1);
+ mdelay(50);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8605, quirk_apalis_plx_gen1);
+#endif /* CONFIG_PCI_FORCE_GEN1 */
+
#ifdef CONFIG_PCI_MSI
/* Some chipsets do not support MSI. We cannot easily rely on setting
* PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually