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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2016-01-06 15:44:07 +0100
committerMax Krummenacher <max.krummenacher@toradex.com>2016-03-08 15:08:10 +0100
commitb69e3aeab332a4a49df7009414cfa4b43fd30e8d (patch)
treebb30ecca1d54515272f72aa4aec34d381162da52
parent10e0417db7be6229a50b621d2dc957f088469241 (diff)
PCI: imx6: fix PCIe EP device self-initialisation
This fixes PCIe EP device self-initialisation in case only a regular reset EP GPIO is used as PERST# which is e.g. the case on our Ixora carrier board by always waiting 20 milliseconds after releasing PERST#. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
-rw-r--r--drivers/pci/host/pci-imx6.c34
1 files changed, 16 insertions, 18 deletions
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index 53234701c2e4..fb01d6110d31 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -363,30 +363,28 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
msleep(1);
if (gpio_is_valid(imx6_pcie->reset_ep_gpio))
gpio_set_value_cansleep(imx6_pcie->reset_ep_gpio, 0);
- /*
- * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
- * for detailed understanding of the PCIe CR reset logic.
- *
- * The PCIe #PERST reset line _MUST_ be connected, otherwise
- * your design does not conform to the specification. You must
- * wait at least 20 mS after de-asserting the #PERST so the
- * EP device can do self-initialisation.
- *
- * In case your #PERST pin is connected to a plain GPIO pin of
- * the CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your
- * board's configuration file and the condition below will
- * handle the rest of the reset toggling.
- */
- mdelay(20);
} else if (gpio_is_valid(imx6_pcie->reset_ep_gpio)) {
gpio_set_value_cansleep(imx6_pcie->reset_ep_gpio, 1);
msleep(100);
gpio_set_value_cansleep(imx6_pcie->reset_ep_gpio, 0);
- } else {
- /* allow the clocks to stabilize */
- udelay(200);
}
+ /*
+ * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
+ * for detailed understanding of the PCIe CR reset logic.
+ *
+ * The PCIe #PERST reset line _MUST_ be connected, otherwise
+ * your design does not conform to the specification. You must
+ * wait at least 20 mS after de-asserting the #PERST so the
+ * EP device can do self-initialisation.
+ *
+ * In case your #PERST pin is connected to a plain GPIO pin of
+ * the CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your
+ * board's configuration file and the condition below will
+ * handle the rest of the reset toggling.
+ */
+ msleep(20);
+
if (imx6_pcie->force_detect_state) {
u32 val;