diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2019-05-23 19:50:41 +0200 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2019-05-28 09:40:50 +0200 |
| commit | 21856d3a865c4982b9eabbc334adf21686b1fc09 (patch) | |
| tree | d76b367660dfbc87850d24574828183349b7591c | |
| parent | 431923eefc517641221fbc2b6f00b5d55115d3e5 (diff) | |
ARM: dts: imx8: apalis-imx8qm: add colibri-vf50-ts configuration
Add the configuration to use the touchscreen hardware provided on
the Apalis iMX8 QM. Keep it in disabled state though to allow the
ADC1 to be used as ADC channels.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts index 1787d29996ad..7e3d1403c274 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts @@ -155,6 +155,25 @@ spdif-in; spdif-out; }; + + touchscreen: vf50-touchscreen { + compatible = "toradex,vf50-touchscreen"; + io-channels = <&adc1 2>,<&adc1 1>, + <&adc1 0>,<&adc1 3>; + xp-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + xm-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + yp-gpios = <&gpio2 17 GPIO_ACTIVE_LOW>; + ym-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio3>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "idle","default"; + pinctrl-0 = <&pinctrl_touchctrl_idle>, <&pinctrl_touchctrl_gpios>; + pinctrl-1 = <&pinctrl_adc1>, <&pinctrl_touchctrl_gpios>; + vf50-ts-min-pressure = <200>; + /* NOTE: you must remove the pinctrl-adc1 from the adc1 + node below to use the touchscreen */ + status = "disabled"; + }; }; &acm { @@ -812,6 +831,22 @@ >; }; + pinctrl_touchctrl_idle: touchctrl_idle { + fsl,pins = < + SC_P_ADC_IN4_LSIO_GPIO3_IO22 0x00000021 + SC_P_ADC_IN5_LSIO_GPIO3_IO23 0x00000021 + >; + }; + + pinctrl_touchctrl_gpios: touchctrl_gpios { + fsl,pins = < + SC_P_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000021 + SC_P_ESAI1_FST_LSIO_GPIO2_IO05 0x00000041 + SC_P_SPI3_SCK_LSIO_GPIO2_IO17 0x00000021 + SC_P_SPI3_CS1_LSIO_GPIO2_IO21 0x00000041 + >; + }; + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { fsl,pins = < SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 |