diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-05-03 14:18:47 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-05-07 08:02:09 +0200 |
| commit | d238aa4153a746f37c24d13554f8861b63dbda5b (patch) | |
| tree | 797a68a72a7d517ef154cc6ad0fad263b73ab5d3 | |
| parent | 22060130df2f99a212208eb90980d0f3a7d1ddd8 (diff) | |
ARM: dts: imx8: apalis-imx8qm: fix enet0_refclk, eth_reset# pin muxing
Fix ENET0_REFCLK as well as ETH_RESET# pin muxing and add a comment
noting us currently using them ENET0 pads in 3.3V mode.
Note: We currently violate specification as NXP has not validated
Gigabit Ethernet operation with them ENET0 pads being in 3.3V mode
(as per note in IMX8QMAEC Rev. H, 8/2018, page 74, section 4.10.5)!
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts index 8651fd936179..c9a17b8719ba 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts @@ -301,7 +301,7 @@ pinctrl_fec1: fec1grp { fsl,pins = < - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 /* Use pads in 3.3V mode */ SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 @@ -316,7 +316,9 @@ SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 - SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x00000021 + SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020 + /* ETH_RESET# */ + SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020 >; }; |