MLK-16890 arm64: dts: imx8qm/qxp: update enet pin setting

enet pins dual voltage pads, bit[0] define the drive strength slection,
bit[4:1] are reserved, and bit[6:5] define the pull down and pull up.

The patch remove the reserved bits setting and pull up the pin.

BuildInfo:
 - SCFW daf9431c, IMX-MKIMAGE 1c6fc7d8, ATF f2547fb
 - U-Boot 2017.03-00097-gd7599cf

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Acked-by: Pandy.gao <pandy.gao@nxp.com>

4 files changed, 106 insertions, 106 deletions

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
index 360e5f01413e..0a3f55486be6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
@@ -219,39 +219,39 @@
 
 		pinctrl_fec1: fec1grp {
 			fsl,pins = <
-				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000048
-				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000048
-				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000048
-				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000048
-				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000048
-				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000048
-				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000048
-				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000048
-				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000048
-				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000048
-				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000048
-				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000048
-				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000048
-				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000048
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000020
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000020
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000020
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000020
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000020
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000020
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000020
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000020
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000020
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000020
 			>;
 		};
 
 		pinctrl_fec2: fec2grp {
 			fsl,pins = <
-				SC_P_ENET1_MDC_CONN_ENET1_MDC			0x06000048
-				SC_P_ENET1_MDIO_CONN_ENET1_MDIO			0x06000048
-				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x06000048
-				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC	0x06000048
-				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x06000048
-				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x06000048
-				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2	0x06000048
-				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3	0x06000048
-				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC	0x06000048
-				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x06000048
-				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x06000048
-				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x06000048
-				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2	0x06000048
-				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3	0x06000048
+				SC_P_ENET1_MDC_CONN_ENET1_MDC			0x06000020
+				SC_P_ENET1_MDIO_CONN_ENET1_MDIO			0x06000020
+				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x06000020
+				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC	0x06000020
+				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x06000020
+				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x06000020
+				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2	0x06000020
+				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3	0x06000020
+				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC	0x06000020
+				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x06000020
+				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x06000020
+				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x06000020
+				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2	0x06000020
+				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3	0x06000020
 			>;
 		};
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
index 8b95e3bf67fc..081d02d1cc6b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
@@ -137,37 +137,37 @@
 	imx8qm-mek {
 		pinctrl_fec1: fec1grp {
 			fsl,pins = <
-				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000048
-				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000048
-				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000048
-				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000048
-				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000048
-				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000048
-				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000048
-				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000048
-				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000048
-				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000048
-				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000048
-				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000048
-				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000048
-				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000048
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000020
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000020
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000020
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000020
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000020
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000020
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000020
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000020
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000020
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000020
 			>;
 		};
 
 		pinctrl_fec2: fec2grp {
 			fsl,pins = <
-				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x06000048
-				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC	0x06000048
-				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x06000048
-				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x06000048
-				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2	0x06000048
-				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3	0x06000048
-				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC	0x06000048
-				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x06000048
-				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x06000048
-				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x06000048
-				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2	0x06000048
-				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3	0x06000048
+				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x06000020
+				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC	0x06000020
+				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x06000020
+				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x06000020
+				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2	0x06000020
+				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3	0x06000020
+				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC	0x06000020
+				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x06000020
+				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x06000020
+				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x06000020
+				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2	0x06000020
+				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3	0x06000020
 			>;
 		};
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
index d97a1183c991..0fdd6fa4c683 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
@@ -191,37 +191,37 @@
 
 		pinctrl_fec1: fec1grp {
 			fsl,pins = <
-				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000048
-				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000048
-				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000048
-				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000048
-				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000048
-				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000048
-				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000048
-				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000048
-				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000048
-				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000048
-				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000048
-				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000048
-				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000048
-				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000048
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000020
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000020
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000020
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000020
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000020
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000020
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000020
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000020
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000020
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000020
 			>;
 		};
 
 		pinctrl_fec2: fec2grp {
 			fsl,pins = <
-				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x06000048
-				SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x06000048
-				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x06000048
-				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x06000048
-				SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x06000048
-				SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x06000048
-				SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x06000048
-				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x06000048
-				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x06000048
-				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x06000048
-				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2	0x06000048
-				SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x06000048
+				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x06000020
+				SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x06000020
+				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x06000020
+				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x06000020
+				SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x06000020
+				SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x06000020
+				SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x06000020
+				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x06000020
+				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x06000020
+				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x06000020
+				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2	0x06000020
+				SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x06000020
 			>;
 		};
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
index 4a5345c6f2b3..bfdcebf46df7 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
@@ -273,37 +273,37 @@
 
 		pinctrl_fec1: fec1grp {
 			fsl,pins = <
-				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000048
-				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000048
-				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000048
-				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000048
-				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000048
-				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000048
-				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000048
-				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000048
-				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000048
-				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000048
-				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000048
-				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000048
-				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000048
-				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000048
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000020
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000020
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000020
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000020
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000020
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000020
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000020
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000020
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000020
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000020
 			>;
 		};
 
 		pinctrl_fec2: fec2grp {
 			fsl,pins = <
-				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x06000048
-				SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x06000048
-				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x06000048
-				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x06000048
-				SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x06000048
-				SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x06000048
-				SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x06000048
-				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x06000048
-				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x06000048
-				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x06000048
-				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2	0x06000048
-				SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x06000048
+				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x06000020
+				SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x06000020
+				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x06000020
+				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x06000020
+				SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x06000020
+				SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x06000020
+				SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x06000020
+				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x06000020
+				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x06000020
+				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x06000020
+				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2	0x06000020
+				SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x06000020
 			>;
 		};