diff options
| author | Viorel Suman <viorel.suman@nxp.com> | 2017-11-20 12:36:51 +0200 |
|---|---|---|
| committer | Viorel Suman <viorel.suman@nxp.com> | 2017-11-20 12:48:12 +0200 |
| commit | 18b1b6c2b479630a3df5ea3a1b7563ffcbcd7294 (patch) | |
| tree | 8ecbe9e0d58206da8e2d9b32b59fc6239a3a4eb2 | |
| parent | 32f5e2b06f17443e019b3cd646d2121f00f19014 (diff) | |
MLK-16738: ARM64: dts: qm-lpddr4-arm2: amix: move SAIs MCLKs to AUD_PLL1
Move AMIX SAIs MCLKs to AUD_PLL1 and double the frequency
in order to support 64k rate.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts index 0a3f55486be6..533543f15d0b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts @@ -174,12 +174,12 @@ &sai6 { assigned-clocks = <&clk IMX8QM_ACM_SAI6_MCLK_SEL>, - <&clk IMX8QM_AUD_PLL0_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, <&clk IMX8QM_AUD_SAI_6_MCLK>; - assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; - assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; fsl,sai-asynchronous; fsl,txm-rxs; status = "okay"; @@ -187,12 +187,12 @@ &sai7 { assigned-clocks = <&clk IMX8QM_ACM_SAI7_MCLK_SEL>, - <&clk IMX8QM_AUD_PLL0_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, <&clk IMX8QM_AUD_SAI_7_MCLK>; - assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; - assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; fsl,sai-asynchronous; fsl,txm-rxs; status = "okay"; |