summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorDominik Sliwa <dominik.sliwa@toradex.com>2018-03-21 17:29:05 +0100
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2018-03-28 18:34:12 +0200
commitd29859e6cf92a866470da451c4d815556ce99188 (patch)
tree0382f216cf409ae9a9b5649a040d9c3bbbff5d49
parent722035cfcd7e238000eafa5803e26072433371c8 (diff)
apalis-tk1:lvds: add option to select 24-bit lvds mode
Add ability to switch between 24.1 and 24.0 lvds modes. Mode description can be found in "Using 24-bpp LVDS Panels with IntelĀ® Mobile Chipsets for Embedded Applications". Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
-rw-r--r--arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-displays.dtsi1
-rw-r--r--arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-v1.2-displays.dtsi1
-rw-r--r--arch/arm/mach-tegra/include/mach/dc.h6
-rw-r--r--drivers/video/tegra/dc/of_dc.c6
-rw-r--r--drivers/video/tegra/dc/sor.c5
-rw-r--r--include/dt-bindings/display/tegra-dc.h4
6 files changed, 22 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-displays.dtsi b/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-displays.dtsi
index 03b686e7c719..cc48334cdc68 100644
--- a/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-displays.dtsi
+++ b/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-displays.dtsi
@@ -20,6 +20,7 @@
nvidia,out-align = <TEGRA_DC_ALIGN_MSB>;
nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>;
nvidia,out-depth = <24>;
+ nvidia,out-lvds-mode = <TEGRA_DC_LVDS_24_1>;
nvidia,out-xres = <1280>;
nvidia,out-yres = <800>;
};
diff --git a/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-v1.2-displays.dtsi b/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-v1.2-displays.dtsi
index b1f21a83f0bc..a7774abcda1d 100644
--- a/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-v1.2-displays.dtsi
+++ b/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-v1.2-displays.dtsi
@@ -20,6 +20,7 @@
nvidia,out-align = <TEGRA_DC_ALIGN_MSB>;
nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>;
nvidia,out-depth = <24>;
+ nvidia,out-lvds-mode = <TEGRA_DC_LVDS_24_1>;
nvidia,out-xres = <1280>;
nvidia,out-yres = <800>;
};
diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h
index c700644d7168..880545833270 100644
--- a/arch/arm/mach-tegra/include/mach/dc.h
+++ b/arch/arm/mach-tegra/include/mach/dc.h
@@ -438,6 +438,11 @@ enum {
TEGRA_DC_TEMPORAL_DITHER,
};
+enum {
+ TEGRA_DC_LVDS_24_1 = 0,
+ TEGRA_DC_LVDS_24_0,
+};
+
typedef u8 tegra_dc_bl_output[256];
typedef u8 *p_tegra_dc_bl_output;
@@ -562,6 +567,7 @@ struct tegra_dc_out {
unsigned align;
unsigned depth;
unsigned dither;
+ unsigned lvds_mode;
const char *default_mode;
diff --git a/drivers/video/tegra/dc/of_dc.c b/drivers/video/tegra/dc/of_dc.c
index 0f047f6388bc..ee1dc1f81f87 100644
--- a/drivers/video/tegra/dc/of_dc.c
+++ b/drivers/video/tegra/dc/of_dc.c
@@ -465,6 +465,12 @@ static int parse_disp_default_out(struct platform_device *ndev,
}
}
+ if (!of_property_read_u32(np, "nvidia,out-lvds-mode", &temp)) {
+ default_out->lvds_mode = temp;
+ OF_DC_LOG("lvds mode %s\n",
+ default_out->lvds_mode);
+ } else
+ default_out->lvds_mode = TEGRA_DC_LVDS_24_1;
/*
* construct fb
*/
diff --git a/drivers/video/tegra/dc/sor.c b/drivers/video/tegra/dc/sor.c
index 65708cffd82f..1326155cd183 100644
--- a/drivers/video/tegra/dc/sor.c
+++ b/drivers/video/tegra/dc/sor.c
@@ -1282,7 +1282,10 @@ void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor,
if (!conforming && (sor->dc->pdata->default_out->depth == 24)) {
tegra_sor_write_field(sor, NV_SOR_LVDS,
NV_SOR_LVDS_ROTDAT_DEFAULT_MASK,
- 6 << NV_SOR_LVDS_ROTDAT_SHIFT);
+ sor->dc->pdata->default_out->lvds_mode ==
+ TEGRA_DC_LVDS_24_1 ?
+ 6 << NV_SOR_LVDS_ROTDAT_SHIFT:
+ 0 << NV_SOR_LVDS_ROTDAT_SHIFT);
tegra_sor_writel(sor, NV_SOR_LANE4_DRIVE_CURRENT(sor->portnum),
0x40);
}
diff --git a/include/dt-bindings/display/tegra-dc.h b/include/dt-bindings/display/tegra-dc.h
index 6f5c316dba15..d8fdcf913407 100644
--- a/include/dt-bindings/display/tegra-dc.h
+++ b/include/dt-bindings/display/tegra-dc.h
@@ -71,5 +71,9 @@
#define TEGRA_DC_OUT_PIN_POL_LOW 0
#define TEGRA_DC_OUT_PIN_POL_HIGH 1
+/* tegra 24-bit lvds mode */
+#define TEGRA_DC_LVDS_24_1 0
+#define TEGRA_DC_LVDS_24_0 1
+
#endif /* __TEGRA_DC_H */