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authorAaron Brice <aaron.brice@datasoft.com>2016-10-06 15:13:04 -0700
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2017-01-11 15:36:43 +0100
commita650cbfc7e981ba24313da0338f4482bef514d44 (patch)
treef2b2fcd71c99e644719f052ca4d55d207ef029c1
parent64086f8ac3e56e50dc60ebd53bde81a15f2f1f2f (diff)
tty: serial: fsl_lpuart: Fix Tx DMA edge case
In the case where head == 0 on the circular buffer, there should be one DMA buffer, not two. The second zero-length buffer would break the lpuart driver, transfer would never complete. Signed-off-by: Aaron Brice <aaron.brice@datasoft.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
-rw-r--r--drivers/tty/serial/fsl_lpuart.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 662e1cb2f3a8..d45087665a6e 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -331,7 +331,7 @@ static void lpuart_dma_tx(struct lpuart_port *sport)
sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
- if (xmit->tail < xmit->head) {
+ if (xmit->tail < xmit->head || xmit->head == 0) {
sport->dma_tx_nents = 1;
sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
} else {