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authorShawn Xiao <b49994@freescale.com>2015-10-28 14:38:58 +0800
committerNitin Garg <nitin.garg@nxp.com>2016-01-14 11:02:11 -0600
commit03f52f63699d7da7ca866693a7674bfe1eb949e7 (patch)
tree5615cd4fbaab2c482b17a917646deb749f87f90f
parentf86a3b3e4aa20819cbe4e2941b2809e2be0f0420 (diff)
MGS-1211 gpu: add GPU for 6sl,6sx,6dl
Add the GPU configuration in the dtsi files for the above three SOCs. date Oct 28, 2015 Signed-off-by: Shawn Xiao <b49994@freescale.com>
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi34
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi33
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi30
3 files changed, 97 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 89ae92f6..9cd5e82 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -63,6 +63,20 @@
};
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x14000000>;
+ linux,cma-default;
+ };
+ };
+
soc {
busfreq {
compatible = "fsl,imx_busfreq";
@@ -80,6 +94,26 @@
fsl,max_ddr_freq = <400000000>;
};
+ gpu@00130000 {
+ compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
+ reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
+ <0x0 0x0>, <0x0 0x8000000>;
+ reg-names = "iobase_3d", "iobase_2d",
+ "phys_baseaddr", "contiguous_mem";
+ interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>,
+ <0 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_3d", "irq_2d";
+ clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>,
+ <&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>,
+ <&clks IMX6QDL_CLK_DUMMY>;
+ clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
+ "gpu2d_clk", "gpu3d_clk",
+ "gpu3d_shader_clk";
+ resets = <&src 0>, <&src 3>;
+ reset-names = "gpu3d", "gpu2d";
+ power-domains = <&gpc 1>;
+ };
+
ocram: sram@00905000 {
compatible = "mmio-sram";
reg = <0x00905000 0x1B000>;
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index ab12b92..46d8fb1 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -8,6 +8,7 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
#include "imx6sl-pinfunc.h"
#include <dt-bindings/clock/imx6sl-clock.h>
@@ -72,6 +73,20 @@
};
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x14000000>;
+ linux,cma-default;
+ };
+ };
+
intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
@@ -929,6 +944,24 @@
reg = <0x021d8000 0x4000>;
status = "disabled";
};
+
+ gpu: gpu@02200000 {
+ compatible = "fsl,imx6sl-gpu", "fsl,imx6q-gpu";
+ reg = <0x02200000 0x4000>, <0x02204000 0x4000>,
+ <0x80000000 0x0>, <0x0 0x8000000>;
+ reg-names = "iobase_2d", "iobase_vg",
+ "phys_baseaddr", "contiguous_mem";
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_2d", "irq_vg";
+ clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
+ <&clks IMX6SL_CLK_MMDC_ROOT>,
+ <&clks IMX6SL_CLK_GPU2D_OVG>;
+ clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
+ "gpu2d_clk";
+ resets = <&src 3>, <&src 3>;
+ reset-names = "gpu2d", "gpuvg";
+ power-domains = <&gpc 1>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 64422b0..47e6677 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -89,6 +89,20 @@
};
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x14000000>;
+ linux,cma-default;
+ };
+ };
+
intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
@@ -216,6 +230,22 @@
clocks = <&clks IMX6SX_CLK_APBH_DMA>;
};
+ gpu: gpu@01800000 {
+ compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu";
+ reg = <0x01800000 0x4000>, <0x80000000 0x0>,
+ <0x0 0x8000000>;
+ reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem";
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_3d";
+ clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>,
+ <&clks 0>;
+ clock-names = "gpu3d_axi_clk", "gpu3d_clk",
+ "gpu3d_shader_clk";
+ resets = <&src 0>;
+ reset-names = "gpu3d";
+ power-domains = <&gpc 1>;
+ };
+
gpmi: gpmi-nand@01806000{
compatible = "fsl,imx6sx-gpmi-nand";
#address-cells = <1>;