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authorRobby Cai <r63905@freescale.com>2015-09-17 09:25:53 +0800
committerNitin Garg <nitin.garg@nxp.com>2016-01-14 11:01:43 -0600
commit2289261b27b1d502a7faaadd527efcffa5fd9c69 (patch)
tree7ebb8f9eca2cdb2b806288e2121edf9a330e3dd7
parentbcfa2f77f70f285e70cebad82692aea8174663c4 (diff)
MLK-11556-7 ARM: dts: imx6dl-sabresd: add epdc support
Add epdc support on i.MX6DL SabreSD board. Add 'compatible', 'clocks' property in common imx6dl.dtsi enable pxp, pmic, epdc in imx6dl-sabresd.dts Signed-off-by: Robby Cai <r63905@freescale.com>
-rw-r--r--arch/arm/boot/dts/imx6dl-sabresd.dts111
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi7
2 files changed, 118 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
index 2181a82..126433f 100644
--- a/arch/arm/boot/dts/imx6dl-sabresd.dts
+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
@@ -16,6 +16,113 @@
compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
};
+&iomuxc {
+ epdc {
+ pinctrl_epdc_0: epdcgrp-0 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x80000000
+ MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x80000000
+ MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x80000000
+ MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x80000000
+ MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x80000000
+ MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x80000000
+ MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x80000000
+ MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x80000000
+ MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x80000000
+ MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x80000000
+ MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x80000000
+ MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x80000000
+ MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x80000000
+ MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x80000000
+ MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x80000000
+ MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x80000000
+ MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x80000000
+ MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x80000000
+ MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x80000000
+ MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x80000000
+ >;
+ };
+ };
+};
+
+&epdc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_epdc_0>;
+ V3P3-supply = <&V3P3_reg>;
+ VCOM-supply = <&VCOM_reg>;
+ DISPLAY-supply = <&DISPLAY_reg>;
+ status = "okay";
+};
+
+&i2c3 {
+ max17135@48 {
+ compatible = "maxim,max17135";
+ reg = <0x48>;
+ vneg_pwrup = <1>;
+ gvee_pwrup = <1>;
+ vpos_pwrup = <2>;
+ gvdd_pwrup = <1>;
+ gvdd_pwrdn = <1>;
+ vpos_pwrdn = <2>;
+ gvee_pwrdn = <1>;
+ vneg_pwrdn = <1>;
+ SENSOR-supply = <&reg_sensor>;
+ gpio_pmic_pwrgood = <&gpio2 21 0>;
+ gpio_pmic_vcom_ctrl = <&gpio3 17 0>;
+ gpio_pmic_wakeup = <&gpio3 20 0>;
+ gpio_pmic_v3p3 = <&gpio2 20 0>;
+ gpio_pmic_intr = <&gpio2 25 0>;
+
+ regulators {
+ DISPLAY_reg: DISPLAY {
+ regulator-name = "DISPLAY";
+ };
+
+ GVDD_reg: GVDD {
+ /* 20v */
+ regulator-name = "GVDD";
+ };
+
+ GVEE_reg: GVEE {
+ /* -22v */
+ regulator-name = "GVEE";
+ };
+
+ HVINN_reg: HVINN {
+ /* -22v */
+ regulator-name = "HVINN";
+ };
+
+ HVINP_reg: HVINP {
+ /* 20v */
+ regulator-name = "HVINP";
+ };
+
+ VCOM_reg: VCOM {
+ regulator-name = "VCOM";
+ /* 2's-compliment, -4325000 */
+ regulator-min-microvolt = <0xffbe0178>;
+ /* 2's-compliment, -500000 */
+ regulator-max-microvolt = <0xfff85ee0>;
+ };
+
+ VNEG_reg: VNEG {
+ /* -15v */
+ regulator-name = "VNEG";
+ };
+
+ VPOS_reg: VPOS {
+ /* 15v */
+ regulator-name = "VPOS";
+ };
+
+ V3P3_reg: V3P3 {
+ regulator-name = "V3P3";
+ };
+ };
+ };
+};
+
&ldb {
lvds-channel@0 {
crtc = "ipu1-di0";
@@ -33,3 +140,7 @@
&mxcfb2 {
status = "okay";
};
+
+&pxp {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 781f86d..89ae92f6 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -98,13 +98,20 @@
};
pxp: pxp@020f0000 {
+ compatible = "fsl,imx6dl-pxp-dma";
reg = <0x020f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_DUMMY>;
+ clock-names = "pxp-axi", "disp-axi";
+ status = "disabled";
};
epdc: epdc@020f4000 {
+ compatible = "fsl,imx6dl-epdc";
reg = <0x020f4000 0x4000>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI1>;
+ clock-names = "epdc_axi", "epdc_pix";
};
lcdif: lcdif@020f8000 {