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authorBai Ping <b51503@freescale.com>2015-08-12 21:55:49 +0800
committerNitin Garg <nitin.garg@nxp.com>2016-01-14 10:59:45 -0600
commit4d1287d313b489b8667dca9247fb2af6a3b2b1e1 (patch)
tree8fe2a96eb008492eed2986348ed202b090720efa
parentcef13fcd3319515e164dec2e19bb30dbba38e83d (diff)
MLK-11343-03 ARM: dts: imx: add clocks in cpu mode
Add pll1, pll1_bypass and pll1_bypass_src clock reference define in dts file. Signed-off-by: Bai Ping <b51503@freescale.com>
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi8
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi8
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi14
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi8
4 files changed, 28 insertions, 10 deletions
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index b2bca91..cb72bcd 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -43,9 +43,13 @@
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
- <&clks IMX6QDL_CLK_PLL1_SYS>;
+ <&clks IMX6QDL_CLK_PLL1_SYS>,
+ <&clks IMX6QDL_CLK_PLL1>,
+ <&clks IMX6QDL_PLL1_BYPASS>,
+ <&clks IMX6QDL_PLL1_BYPASS_SRC>;
clock-names = "arm", "pll2_pfd2_396m", "step",
- "pll1_sw", "pll1_sys";
+ "pll1_sw", "pll1_sys", "pll1",
+ "pll1_bypass", "Pll1_bypass_src";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 7b4187b..6fa57cc 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -47,9 +47,13 @@
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
- <&clks IMX6QDL_CLK_PLL1_SYS>;
+ <&clks IMX6QDL_CLK_PLL1_SYS>,
+ <&clks IMX6QDL_CLK_PLL1>,
+ <&clks IMX6QDL_PLL1_BYPASS>,
+ <&clks IMX6QDL_PLL1_BYPASS_SRC>;
clock-names = "arm", "pll2_pfd2_396m", "step",
- "pll1_sw", "pll1_sys";
+ "pll1_sw", "pll1_sys", "pll1",
+ "pll1_bypass", "pll1_bypass_src";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 81f39d9..f15e733 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -55,11 +55,17 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
- clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
- <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
- <&clks IMX6SL_CLK_PLL1_SYS>;
+ clocks = <&clks IMX6SL_CLK_ARM>,
+ <&clks IMX6SL_CLK_PLL2_PFD2>,
+ <&clks IMX6SL_CLK_STEP>,
+ <&clks IMX6SL_CLK_PLL1_SW>,
+ <&clks IMX6SL_CLK_PLL1_SYS>,
+ <&clks IMX6SL_CLK_PLL1>,
+ <&clks IMX6SL_PLL1_BYPASS>,
+ <&clks IMX6SL_PLL1_BYPASS_SRC>;
clock-names = "arm", "pll2_pfd2_396m", "step",
- "pll1_sw", "pll1_sys";
+ "pll1_sw", "pll1_sys", "pll1", "pll1_bypass",
+ "pll1_bypass_src";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 5efdb23..f4aed91 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -75,9 +75,13 @@
<&clks IMX6SX_CLK_PLL2_PFD2>,
<&clks IMX6SX_CLK_STEP>,
<&clks IMX6SX_CLK_PLL1_SW>,
- <&clks IMX6SX_CLK_PLL1_SYS>;
+ <&clks IMX6SX_CLK_PLL1_SYS>,
+ <&clks IMX6SX_CLK_PLL1>,
+ <&clks IMX6SX_PLL7_BYPASS>,
+ <&clks IMX6SX_PLL7_BYPASS_SRC>;
clock-names = "arm", "pll2_pfd2_396m", "step",
- "pll1_sw", "pll1_sys";
+ "pll1_sw", "pll1_sys", "pll1",
+ "pll1_bypass", "pll1_bypass_src";
arm-supply = <&reg_arm>;
soc-supply = <&reg_soc>;
};