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authorSandor Yu <R01008@freescale.com>2015-09-21 17:34:34 +0800
committerNitin Garg <nitin.garg@nxp.com>2016-01-14 11:01:36 -0600
commitc15d2cd300e1ef5e5be369f7308090112fbfc367 (patch)
treeaf31cecc032c32a29ea76c77105e090712c92508
parent9bd019f58541793e9e291bd464eb5e9b673f41de (diff)
MLK-11508-5: dts: Add imx v4l2 capture driver
Add imx v4l2 capture driver. Signed-off-by: Sandor Yu <R01008@freescale.com>
-rw-r--r--arch/arm/boot/dts/Makefile4
-rw-r--r--arch/arm/boot/dts/imx6dl-sabreauto.dts14
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi16
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi13
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi41
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi146
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi44
-rw-r--r--arch/arm/boot/dts/imx6sl-evk-csi.dts21
-rw-r--r--arch/arm/boot/dts/imx6sl-evk.dts66
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi6
-rw-r--r--arch/arm/boot/dts/imx6sx-19x19-arm2-csi.dts25
-rw-r--r--arch/arm/boot/dts/imx6sx-sabreauto.dts19
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dtsi79
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi8
-rw-r--r--arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts22
-rw-r--r--arch/arm/boot/dts/imx6ul-9x9-evk-csi.dts22
-rw-r--r--arch/arm/boot/dts/imx7d-sdb.dts44
17 files changed, 542 insertions, 48 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d18f8a5..180b49b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -315,6 +315,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
imx6sl-evk-ldo.dtb \
+ imx6sl-evk-csi.dtb \
imx6sl-evk-uart.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SX) += \
@@ -327,6 +328,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-sdb-sai.dtb \
imx6sx-19x19-arm2.dtb \
imx6sx-19x19-arm2-ldo.dtb
+ imx6sx-19x19-arm2-csi.dtb
dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-ddr3-arm2.dtb \
imx6ul-14x14-ddr3-arm2-gpmi-weim.dtb \
@@ -334,8 +336,10 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-ddr3-arm2-spdif.dtb \
imx6ul-14x14-ddr3-arm2-wm8958.dtb \
imx6ul-14x14-evk.dtb \
+ imx6ul-14x14-evk-csi.dtb \
imx6ul-14x14-lpddr2-arm2.dtb \
imx6ul-9x9-evk.dtb \
+ imx6ul-9x9-evk-csi.dtb \
imx6ul-9x9-evk-ldo.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-12x12-lpddr3-arm2.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
index a6ce7b4..bd13b35 100644
--- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -15,3 +15,17 @@
model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
};
+&ldb {
+ lvds-channel@0 {
+ crtc = "ipu1-di0";
+ };
+ lvds-channel@1 {
+ crtc = "ipu1-di1";
+ };
+};
+&mxcfb1 {
+ status = "okay";
+};
+&mxcfb2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 69cee0e..781f86d 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -91,6 +91,12 @@
compatible = "fsl,imx6dl-iomuxc";
};
+ dcic2: dcic@020e8000 {
+ clocks = <&clks IMX6QDL_CLK_DCIC1 >,
+ <&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/
+ clock-names = "dcic", "disp-axi";
+ };
+
pxp: pxp@020f0000 {
reg = <0x020f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
@@ -108,6 +114,16 @@
};
aips2: aips-bus@02100000 {
+ mipi_dsi: mipi@021e0000 {
+ compatible = "fsl,imx6dl-mipi-dsi";
+ reg = <0x021e0000 0x4000>;
+ interrupts = <0 102 0x04>;
+ gpr = <&gpr>;
+ clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>;
+ clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
+ status = "disabled";
+ };
+
i2c4: i2c@021f8000 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 3d54155..d14f759 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -14,6 +14,7 @@
/ {
aliases {
+ ipu1 = &ipu2;
spi4 = &ecspi5;
};
@@ -177,6 +178,18 @@
};
};
+ aips-bus@02100000 { /* AIPS2 */
+ mipi_dsi: mipi@021e0000 {
+ compatible = "fsl,imx6q-mipi-dsi";
+ reg = <0x021e0000 0x4000>;
+ interrupts = <0 102 0x04>;
+ gpr = <&gpr>;
+ clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>;
+ clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
+ status = "disabled";
+ };
+ };
+
sata: sata@02200000 {
compatible = "fsl,imx6q-ahci";
reg = <0x02200000 0x4000>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index b73cf01..bdae964 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -69,6 +69,14 @@
regulator-always-on;
};
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
reg_si4763_vio1: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
@@ -206,6 +214,14 @@
status = "okay";
};
+ v4l2_cap_0 {
+ compatible = "fsl,imx6q-v4l2-capture";
+ ipu_id = <0>;
+ csi_id = <0>;
+ mclk_source = <0>;
+ status = "okay";
+ };
+
v4l2_out {
compatible = "fsl,mxc_v4l2_output";
status = "okay";
@@ -441,6 +457,24 @@
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
+ adv7180: adv7180@21 {
+ compatible = "adv,adv7180";
+ reg = <0x21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_1>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&reg_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */
+ AVDD-supply = <&reg_3p3v>; /* 1.8v */
+ DVDD-supply = <&reg_3p3v>; /* 1.8v */
+ PVDD-supply = <&reg_3p3v>; /* 1.8v */
+ pwn-gpios = <&max7310_b 2 0>;
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <0>;
+ cvbs = <1>;
+ };
+
isl29023@44 {
compatible = "fsl,isl29023";
reg = <0x44>;
@@ -503,12 +537,17 @@
pinctrl_hog: hoggrp {
fsl,pins = <
- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1f059
MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
+ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000
+ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x80000000
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x17059
+ MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x17059
>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 5c41442..a9752bf 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -97,6 +97,13 @@
startup-delay-us = <500>;
enable-active-high;
};
+
+ reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on {
+ compatible = "regulator-fixed";
+ regulator-name = "mipi_dsi_pwr_on";
+ gpio = <&gpio6 14 0>;
+ enable-active-high;
+ };
};
gpio-keys {
@@ -219,15 +226,20 @@
status = "okay";
};
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
+ v4l2_cap_0 {
+ compatible = "fsl,imx6q-v4l2-capture";
+ ipu_id = <0>;
+ csi_id = <0>;
+ mclk_source = <0>;
+ status = "okay";
+ };
- red {
- gpios = <&gpio1 2 0>;
- default-state = "on";
- };
+ v4l2_cap_1 {
+ compatible = "fsl,imx6q-v4l2-capture";
+ ipu_id = <0>;
+ csi_id = <1>;
+ mclk_source = <0>;
+ status = "okay";
};
v4l2_out {
@@ -235,6 +247,12 @@
status = "okay";
};
+ mipi_dsi_reset: mipi-dsi-reset {
+ compatible = "gpio-reset";
+ reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <50>;
+ #reset-cells = <0>;
+ };
};
&audmux {
@@ -248,6 +266,11 @@
soc-supply = <&sw1c_reg>;
};
+&clks {
+ fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
+ fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
+};
+
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 9 0>;
@@ -276,6 +299,18 @@
fsl,ldo-bypass = <1>;
};
+&dcic1 {
+ dcic_id = <0>;
+ dcic_mux = "dcic-hdmi";
+ status = "okay";
+};
+
+&dcic2 {
+ dcic_id = <1>;
+ dcic_mux = "dcic-lvds1";
+ status = "okay";
+};
+
&hdmi_audio {
status = "okay";
};
@@ -337,6 +372,24 @@
interrupts = <18 8>;
interrupt-route = <1>;
};
+
+ ov564x: ov564x@3c {
+ compatible = "ovti,ov564x";
+ reg = <0x3c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_2>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+ AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3,
+ on rev B board is VGEN5 */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */
+ rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <0>;
+ };
};
&i2c2 {
@@ -345,12 +398,12 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
- egalax_ts@04 {
- compatible = "eeti,egalax_ts";
- reg = <0x04>;
- interrupt-parent = <&gpio6>;
- interrupts = <8 2>;
- wakeup-gpios = <&gpio6 8 0>;
+ max11801@48 {
+ compatible = "maxim,max11801";
+ reg = <0x48>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <26 2>;
+ work-mode = <1>;/*DCM mode*/
};
pmic: pfuze100@08 {
@@ -456,6 +509,22 @@
compatible = "fsl,imx6-hdmi-i2c";
reg = <0x50>;
};
+
+ ov564x_mipi: ov564x_mipi@3c { /* i2c2 driver */
+ compatible = "ovti,ov564x_mipi";
+ reg = <0x3c>;
+ clocks = <&clks 201>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+ AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
+ rev B board is VGEN5 */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */
+ rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */
+ csi_id = <1>;
+ mclk = <24000000>;
+ mclk_source = <0>;
+ };
};
&i2c3 {
@@ -499,22 +568,32 @@
imx6qdl-sabresd {
pinctrl_hog: hoggrp {
fsl,pins = <
- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
- MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000
- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
+ MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
+ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000
MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000
- MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
+ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
+ MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
>;
};
@@ -653,6 +732,8 @@
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000
>;
};
@@ -813,6 +894,23 @@
};
};
+&mipi_csi {
+ status = "okay";
+ ipu_id = <0>;
+ csi_id = <1>;
+ v_channel = <0>;
+ lanes = <2>;
+};
+
+&mipi_dsi {
+ dev_id = <0>;
+ disp_id = <1>;
+ lcd_panel = "TRULY-WVGA";
+ disp-power-on-supply = <&reg_mipi_dsi_pwr_on>;
+ resets = <&mipi_dsi_reset>;
+ status = "okay";
+};
+
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 8b69049..e63bfb6 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -863,13 +863,23 @@
};
dcic1: dcic@020e4000 {
+ compatible = "fsl,imx6q-dcic";
reg = <0x020e4000 0x4000>;
interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>;
+ clock-names = "dcic", "disp-axi";
+ gpr = <&gpr>;
+ status = "disabled";
};
dcic2: dcic@020e8000 {
+ compatible = "fsl,imx6q-dcic";
reg = <0x020e8000 0x4000>;
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>;
+ clock-names = "dcic", "disp-axi";
+ gpr = <&gpr>;
+ status = "disabled";
};
sdma: sdma@020ec000 {
@@ -1118,30 +1128,24 @@
status = "disabled";
};
- mipi_csi: mipi@021dc000 {
+ mipi_csi: mipi_csi@021dc000 { /* MIPI-CSI */
+ compatible = "fsl,imx6q-mipi-csi2";
reg = <0x021dc000 0x4000>;
+ interrupts = <0 100 0x04>, <0 101 0x04>;
+ clocks = <&clks IMX6QDL_CLK_HSI_TX>,
+ <&clks IMX6QDL_CLK_EMI_SEL>,
+ <&clks IMX6QDL_CLK_VIDEO_27M>;
+ /* Note: clks 138 is hsi_tx, however, the dphy_c
+ * hsi_tx and pll_refclk use the same clk gate.
+ * In current clk driver, open/close clk gate do
+ * use hsi_tx for a temporary debug purpose.
+ */
+ clock-names = "dphy_clk", "pixel_clk", "cfg_clk";
+ status = "disabled";
};
- mipi_dsi: mipi@021e0000 {
- #address-cells = <1>;
- #size-cells = <0>;
+ mipi@021e0000 { /* MIPI-DSI */
reg = <0x021e0000 0x4000>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- };
-
- port@1 {
- reg = <1>;
-
- };
- };
};
vdoa@021e4000 {
diff --git a/arch/arm/boot/dts/imx6sl-evk-csi.dts b/arch/arm/boot/dts/imx6sl-evk-csi.dts
new file mode 100644
index 0000000..56d824b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-evk-csi.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6sl-evk.dts"
+
+&csi {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&epdc {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 171d7d7..9bfed70 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -130,6 +130,14 @@
soc-supply = <&sw1c_reg>;
};
+&csi {
+ port {
+ csi_ep: endpoint {
+ remote-endpoint = <&ov5640_ep>;
+ };
+ };
+};
+
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 11 0>;
@@ -292,6 +300,34 @@
};
};
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "disabled";
+
+ ov5640: ov5640@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_csi_0>;
+ clocks = <&clks IMX6SL_CLK_CSI>;
+ clock-names = "csi_mclk";
+ AVDD-supply = <&vgen6_reg>; /* 2.8v */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ pwn-gpios = <&gpio1 25 1>;
+ rst-gpios = <&gpio1 26 0>;
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <0>;
+ port {
+ ov5640_ep: endpoint {
+ remote-endpoint = <&csi_ep>;
+ };
+ };
+ };
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
@@ -371,6 +407,13 @@
>;
};
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1
+ MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
pinctrl_kpp: kppgrp {
fsl,pins = <
MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
@@ -574,6 +617,27 @@
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
>;
};
+
+ pinctrl_csi_0: csigrp-0 {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x110b0
+ MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0
+ MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x110b0
+ MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x110b0
+ MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0
+ MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0
+ MX6SL_PAD_EPDC_D7__CSI_DATA07 0x110b0
+ MX6SL_PAD_EPDC_D6__CSI_DATA06 0x110b0
+ MX6SL_PAD_EPDC_D5__CSI_DATA05 0x110b0
+ MX6SL_PAD_EPDC_D4__CSI_DATA04 0x110b0
+ MX6SL_PAD_EPDC_D3__CSI_DATA03 0x110b0
+ MX6SL_PAD_EPDC_D2__CSI_DATA02 0x110b0
+ MX6SL_PAD_EPDC_D1__CSI_DATA01 0x110b0
+ MX6SL_PAD_EPDC_D0__CSI_DATA00 0x110b0
+ MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
+ MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000
+ >;
+ };
};
};
@@ -601,7 +665,7 @@
status = "okay";
display0: display0 {
- bits-per-pixel = <32>;
+ bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 9f007fa..05e8428 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -695,8 +695,14 @@
};
csi: csi@020e4000 {
+ compatible = "fsl,imx6s-csi";
reg = <0x020e4000 0x4000>;
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_DUMMY>,
+ <&clks IMX6SL_CLK_DUMMY>,
+ <&clks IMX6SL_CLK_DUMMY>;
+ clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+ status = "disabled";
};
spdc: spdc@020e8000 {
diff --git a/arch/arm/boot/dts/imx6sx-19x19-arm2-csi.dts b/arch/arm/boot/dts/imx6sx-19x19-arm2-csi.dts
new file mode 100644
index 0000000..4119395
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-19x19-arm2-csi.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6sx-19x19-arm2.dts"
+
+&esai {
+ /* pin conflict with sai */
+ status = "disabled";
+};
+
+&sai1 {
+ status = "disabled";
+};
+
+&i2c2 {
+ ov5640: ov5640@3c {
+ status = "okay";
+ };
+};
+
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index c68589b..9fc77c7 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -332,3 +332,22 @@
};
};
};
+&csi2 {
+ status = "okay";
+ port {
+ csi2_ep: endpoint {
+ remote-endpoint = <&vadc_ep>;
+ };
+ };
+};
+
+&vadc {
+ vadc_in = <0>;
+ csi_id = <1>;
+ status = "okay";
+ port {
+ vadc_ep: endpoint {
+ remote-endpoint = <&csi2_ep>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index 7830150..e12b7a9 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -208,6 +208,25 @@
};
};
+&csi1 {
+ status = "okay";
+
+ port {
+ csi1_ep: endpoint {
+ remote-endpoint = <&ov5640_ep>;
+ };
+ };
+};
+
+&csi2 {
+ status = "okay";
+ port {
+ csi2_ep: endpoint {
+ remote-endpoint = <&vadc_ep>;
+ };
+ };
+};
+
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
@@ -216,6 +235,34 @@
status = "okay";
};
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ ov5640: ov5640@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_csi_0>;
+ clocks = <&clks IMX6SX_CLK_CSI>;
+ clock-names = "csi_mclk";
+ AVDD-supply = <&vgen3_reg>; /* 2.8v */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ pwn-gpios = <&gpio3 28 1>;
+ rst-gpios = <&gpio3 27 0>;
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <0>;
+ port {
+ ov5640_ep: endpoint {
+ remote-endpoint = <&csi1_ep>;
+ };
+ };
+ };
+};
+
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
@@ -417,6 +464,27 @@
>;
};
+ pinctrl_csi_0: csigrp-0 {
+ fsl,pins = <
+ MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0
+ MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0
+ MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0
+ MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0
+ MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0
+ MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0
+ MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0
+ MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0
+ MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0
+ MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0
+ MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0
+ MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0
+ MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0
+ MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0
+ MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000
+ MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000
+ >;
+ };
+
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
@@ -694,3 +762,14 @@
};
};
};
+
+&vadc {
+ vadc_in = <0>;
+ csi_id = <1>;
+ status = "okay";
+ port {
+ vadc_ep: endpoint {
+ remote-endpoint = <&csi2_ep>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index c429ee3..d118910 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -1145,12 +1145,14 @@
ranges;
csi1: csi@02214000 {
+ compatible = "fsl,imx6s-csi";
reg = <0x02214000 0x4000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
<&clks IMX6SX_CLK_CSI>,
<&clks IMX6SX_CLK_DCIC1>;
- clock-names = "disp-axi", "csi_mclk", "dcic";
+ clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+ power-domains = <&gpc 2>;
status = "disabled";
};
@@ -1164,12 +1166,14 @@
};
csi2: csi@0221c000 {
+ compatible = "fsl,imx6s-csi";
reg = <0x0221c000 0x4000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
<&clks IMX6SX_CLK_CSI>,
<&clks IMX6SX_CLK_DCIC2>;
- clock-names = "disp-axi", "csi_mclk", "dcic";
+ clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+ power-domains = <&gpc 2>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts b/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts
new file mode 100644
index 0000000..f2bf26f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ul-14x14-evk.dts"
+
+
+&csi {
+ status = "okay";
+};
+
+&ov5640 {
+ status = "okay";
+};
+
+&sim2 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx6ul-9x9-evk-csi.dts b/arch/arm/boot/dts/imx6ul-9x9-evk-csi.dts
new file mode 100644
index 0000000..2177807
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-9x9-evk-csi.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ul-9x9-evk.dts"
+
+
+&csi {
+ status = "okay";
+};
+
+&ov5640 {
+ status = "okay";
+};
+
+&sim2 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index aeebef5..61401ee 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -130,6 +130,17 @@
assigned-clock-rates = <884736000>;
};
+&csi1 {
+ csi-mux-mipi = <&gpr 0x14 4>;
+ status = "okay";
+
+ port {
+ csi_ep: endpoint {
+ remote-endpoint = <&csi_mipi_ep>;
+ };
+ };
+};
+
&epxp {
status = "okay";
};
@@ -176,6 +187,23 @@
status = "okay";
};
+&mipi_csi {
+ clock-frequency = <240000000>;
+ status = "okay";
+ port {
+ mipi_sensor_ep: endpoint1 {
+ remote-endpoint = <&ov5647_mipi_ep>;
+ data-lanes = <2>;
+ csis-hs-settle = <13>;
+ csis-wclk;
+ };
+
+ csi_mipi_ep: endpoint2 {
+ remote-endpoint = <&csi_ep>;
+ };
+ };
+};
+
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@@ -316,6 +344,22 @@
clock-names = "mclk";
wlf,shared-lrclk;
};
+
+ ov5647_mipi: ov5647_mipi@36 {
+ compatible = "ovti,ov5647_mipi";
+ reg = <0x36>;
+ clocks = <&clks IMX7D_CLK_DUMMY>;
+ clock-names = "csi_mclk";
+ csi_id = <0>;
+ pwn-gpios = <&gpio_spi 7 GPIO_ACTIVE_HIGH>;
+ mclk = <24000000>;
+ mclk_source = <0>;
+ port {
+ ov5647_mipi_ep: endpoint {
+ remote-endpoint = <&mipi_sensor_ep>;
+ };
+ };
+ };
};
&gpmi {