MLK-18535-13 dt-bindings: display: bridge: add sec-dsim bindings

Add the device-tree bindings for the display bridge
Samsung MIPI DSIM on i.MX platforms.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>

1 files changed, 57 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt
new file mode 100644
index 000000000000..9bc5e9dd2539
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt
@@ -0,0 +1,57 @@
+Samsung MIPI DSIM bridge bindings
+
+The MIPI DSIM host controller drives the video signals from
+display controller to video peripherals using DSI protocol.
+This is an un-managed DSI bridge. In order to use this bridge,
+an encoder or bridge must be implemented to manage the platform
+specific initializations.
+
+Required properties:
+- compatible: 		"fsl,imx8mm-mipi-dsim"
+- reg: 			the register range of the MIPI DSIM controller
+- interrupts: 		the interrupt number for this module
+- clock, clock-names: 	phandles to the MIPI-DSI clocks described in
+  Documentation/devicetree/bindings/clock/clock-bindings.txt
+	"cfg"		- DSIM access clock
+	"pll-ref"	- DSIM PHY PLL reference clock
+- assigned-clocks:	phandles to clocks that requires initial configuration
+- assigned-clock-rates:	rates of the clocks that requires initial configuration
+- port: 		input and output port nodes with endpoint definitions as
+			defined in Documentation/devicetree/bindings/graph.txt;
+			the input port should be connected to an encoder or a
+			bridge that manages this MIPI DSIM host and the output
+			port should be connected to a panel or a bridge input
+			port
+
+Optional properties:
+-dsi-gpr:		a phandle which provides the MIPI DSIM control and gpr registers
+
+example:
+	mipi_dsi: mipi_dsi@32E10000 {
+		compatible = "fsl,imx8mm-mipi-dsim";
+		reg = <0x0 0x32e10000 0x0 0x400>;
+		clocks = <&clk IMX8MM_CLK_DSI_CORE_DIV>,
+			 <&clk IMX8MM_CLK_DSI_PHY_REF_DIV>;
+		clock-names = "cfg", "pll-ref";
+		assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE_SRC>,
+				  <&clk IMX8MM_CLK_DSI_PHY_REF_SRC>;
+		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
+					 <&clk IMX8MM_VIDEO_PLL1_OUT>;
+		assigned-clock-rates = <266000000>, <594000000>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		dsi-gpr = <&dispmix_gpr>;
+		status = "disabled";
+
+		port@0 {
+			dsim_from_lcdif: endpoint {
+				remote-endpoint = <&lcdif_to_dsim>;
+			};
+		};
+
+		port@1 {
+			dsim_to_adv7535: endpoint {
+				remote-endpoint = <&adv7535_from_dsim>;
+			};
+		};
+
+	};