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authorVignesh Raghavendra <vigneshr@ti.com>2019-04-23 16:18:13 +0530
committerHan Xu <han.xu@nxp.com>2019-05-07 11:12:10 -0500
commitc5ac8a7ccc453a8aa89ceb12e7b1f81536831f3f (patch)
tree7321c0cbf47d88797b8d3dce7f7caaaedea1db96 /Documentation/devicetree/bindings/mtd
parent7dcceaba83187a419acdfbb46aa985c31f18857e (diff)
dt-bindings: mtd: Add bindings for TI's AM654 HyperBus memory controller
Add binding documentation for TI's HyperBus memory controller present on AM654 SoC. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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+Bindings for HyperBus Memory Controller (HBMC) on TI's K3 family of SoCs
+
+Required properties:
+- compatible : "ti,am654-hbmc" for AM654 SoC
+- reg : Two entries:
+ First entry pointed to the register space of HBMC controller
+ Second entry pointing to the memory map region dedicated for
+ MMIO access to attached flash devices
+- ranges : Address range allocated for each chipselect in the MMIO space
+
+Optional properties:
+- mux-controls : phandle to the multiplexer that controls selection of
+ HBMC vs OSPI. Mux state of 1 indicates HBMC is selected.
+
+Example:
+
+ hbmc: hbmc@47034000 {
+ compatible = "ti,am654-hbmc";
+ reg = <0x0 0x47034000 0x0 0x100>,
+ <0x5 0x00000000 0x1 0x0000000>;
+ power-domains = <&k3_pds 55>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */
+ <0x1 0x5 0x04000000 0x4000000>; /* CS1 - 64MB
+
+ /* Slave flash node */
+ flash@0 {
+ compatible = "cypress,hyperflash";
+ reg = <0x0 0x4000000>;
+ };
+ };