diff options
| author | Liu Ying <victor.liu@nxp.com> | 2017-09-12 17:28:48 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:33:40 +0800 |
| commit | d021eabcd792859af2c76404f4141dd3cc41c435 (patch) | |
| tree | 604f29cbc4d4678411cdde5b2625a080f1e68547 /Documentation/devicetree/bindings | |
| parent | 6dd5c1b4c9a59ccd4b1596619fde10f699f522f8 (diff) | |
MLK-19413-1 dt-bindings: display: imx-drm: Add pixel combiner descriptions
Pixel combiner found in i.MX8 SoCs may combine two display
streams(one master and the other slave) to drive a high
pixel rate display. This patch adds DT property descriptions
in imx-drm DT documentation for pixel combiner.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings')
| -rw-r--r-- | Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt index 4c9256f20717..a7b35da0a100 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt @@ -132,6 +132,7 @@ Required properties: - power-domains: phandle pointing to power domain. - fsl,dpr-channels: phandles to the DPR channels attached to this DPU, sorted by memory map addresses. Only valid for i.MX8qm and i.MX8qxp. +- fsl,pixel-combiner: phandle to the pixel combiner unit attached to this DPU. Optional properties: - port@[0-1]: Port nodes with endpoint definitions as defined in Documentation/devicetree/bindings/media/video-interfaces.txt. @@ -171,6 +172,7 @@ dpu: dpu@56180000 { fsl,dpr-channels = <&dpr1_channel1>, <&dpr1_channel2>, <&dpr1_channel3>, <&dpr2_channel1>, <&dpr2_channel2>, <&dpr2_channel3>; + fsl,pixel-combiner = <&pixel_combiner1>; dpu1_disp1: port@1 { reg = <1>; @@ -301,6 +303,22 @@ example: }; }; +Freescale i.MX8 PC (Pixel Combiner) +============================================= +Required properties: +- compatible: should be "fsl,<chip>-pixel-combiner" +- reg: should be register base and length as documented in the + datasheet +- power-domains: phandle pointing to power domain + +example: + +pixel-combiner@56020000 { + compatible = "fsl,imx8qm-pixel-combiner"; + reg = <0x0 0x56020000 0x0 0x10000>; + power-domains = <&pd_dc0>; +}; + Freescale i.MX8 PRG (Prefetch Resolve Gasket) ============================================= Required properties: |