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authorNava kishore Manne <nava.manne@xilinx.com>2016-10-12 13:17:28 +0530
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-10-27 16:00:32 +0200
commit78c22449f2d32aafd8804047f7e3bee4926b52eb (patch)
treecb18e3c218640c81a2fbc66a98564af46169e431 /Documentation/devicetree
parent0267a4ff9836a1a4e59044db5bb8cdaddb986d3f (diff)
devicetree: bindings: uart: Add new compatible string for ZynqMP
This patch Adds the new compatible string for ZynqMP SoC. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/serial/cdns,uart.txt4
1 files changed, 3 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.txt b/Documentation/devicetree/bindings/serial/cdns,uart.txt
index a3eb154c32ca..227bb770b027 100644
--- a/Documentation/devicetree/bindings/serial/cdns,uart.txt
+++ b/Documentation/devicetree/bindings/serial/cdns,uart.txt
@@ -1,7 +1,9 @@
Binding for Cadence UART Controller
Required properties:
-- compatible : should be "cdns,uart-r1p8", or "xlnx,xuartps"
+- compatible :
+ Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
+ Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
- reg: Should contain UART controller registers location and length.
- interrupts: Should contain UART controller interrupts.
- clocks: Must contain phandles to the UART clocks