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authorAndrew Jeffery <andrew@aj.id.au>2016-06-10 16:46:36 +0930
committerLinus Walleij <linus.walleij@linaro.org>2016-06-13 09:33:42 +0200
commit73f8fed031d51868b57835cb1616c6aeea20a8d0 (patch)
tree23a2d58cdc2ba3f43f7dbd8b1636ac97282a67cf /Documentation/pinctrl.txt
parenteef06737e5dd9baa1ec8606f74356575ab15291d (diff)
pinctrl: Reflow/wrap paragraph describing GPIO interaction
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'Documentation/pinctrl.txt')
-rw-r--r--Documentation/pinctrl.txt14
1 files changed, 7 insertions, 7 deletions
diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
index 07d102c3d05a..6414a613cb8a 100644
--- a/Documentation/pinctrl.txt
+++ b/Documentation/pinctrl.txt
@@ -286,13 +286,13 @@ see the section named "pin control requests from drivers" and
"drivers needing both pin control and GPIOs" below for details. But in some
situations a cross-subsystem mapping between pins and GPIOs is needed.
-Since the pin controller subsystem has its pinspace local to the pin
-controller we need a mapping so that the pin control subsystem can figure out
-which pin controller handles control of a certain GPIO pin. Since a single
-pin controller may be muxing several GPIO ranges (typically SoCs that have
-one set of pins, but internally several GPIO silicon blocks, each modelled as
-a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
-instance like this:
+Since the pin controller subsystem has its pinspace local to the pin controller
+we need a mapping so that the pin control subsystem can figure out which pin
+controller handles control of a certain GPIO pin. Since a single pin controller
+may be muxing several GPIO ranges (typically SoCs that have one set of pins,
+but internally several GPIO silicon blocks, each modelled as a struct
+gpio_chip) any number of GPIO ranges can be added to a pin controller instance
+like this:
struct gpio_chip chip_a;
struct gpio_chip chip_b;