video: tegra: dc: direct dc node search

Use of_find_node_by_path for dc child node search
instead of_find_node_by_name.
of_find_node_by_name search node from current node point
to next all. Since dc0 node is preceding dc1 sibling node,
even dc1 node has certain child node only in device tree,
this can be searched from dc0 node point as well, that is
not desired result. Also, move tmds configuration properties
underneath hdmi node, since it is hdmi property.

Bug 1371533
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>

Change-Id: Iaffa42629652eb875f8ccc69acba7e290fc55650
Reviewed-on: http://git-master/r/344227
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Min-wuk Lee <mlee@nvidia.com>
Tested-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

4 files changed, 46 insertions, 46 deletions

diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt b/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt
index a7a18a7a9b18..5b4c34cb42b0 100644
--- a/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt
+++ b/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt
@@ -66,29 +66,6 @@ NVIDIA Tegra114 Display Controller
    For hdmi out-type case, depth selection is only valid for hdmi fb console mode,
    otherwise, BASE_COLOR_SIZE888 is chosen as a default.
 
- 1.B.i) NVIDIA Display Controller TMDS configurations
- This must be contained in dc-default-out parent node. This includes tmds configurations.
-
- Required properties:
- - name: Should be "nvidia,out-tmds-cfg"
-
- - Child nodes represent tmds configurations. Several configurations can be prepared.
-
- 1.B.i.x) NVIDIA Display Controller TMDS configuration
- This must be contained in nvidia,out-tmds-cfg parent node. This includes tmds configuration.
-
- Required properties:
- - name: Can be arbitrary, but each sibling node should have unique name.
- - pclk: pixel clk required in tmds table for each mode.
- - pll0: See HDMI_NV_PDISP_SOR_PLL0_0 in Tegra TRM.
- - pll1: See HDMI_NV_PDISP_SOR_PLL1_0 in Tegra TRM.
- - pe-current: Individual lane pre-emphasis current control (4bits per lane)
-   See HDMI_NV_PDISP_PE_CURRENT_0 in Tegra TRM.
- - drive-current: TMDS per-lane I/O current control.
-   See HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_0 in Tegra TRM.
- - peak-current: New pad controls for 28nm macro TMDS_X4_HP 8 bits per lane.
-   See HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_0 in Tegra TRM.
-
 1.C) NVIDIA Display Controller framebuffer data
  This must be contained in dc parent node. This is required framebuffer data.
 
diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt b/Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt
index 36617e7b898b..03c320a4b1a4 100644
--- a/Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt
+++ b/Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt
@@ -23,6 +23,29 @@ NVIDIA TEGRA114 High Definition Multimedia Interface
  - regulator names for supply voltage, PLL and hdmi 5V source should be avdd_hdmi, avdd_hdmi_pll,
    vdd_hdmi_5v0, respectively.
 
+ 1.B) NVIDIA HDMI TMDS configurations
+ This must be contained in hdmi parent node. This includes tmds configurations.
+
+ Required properties:
+ - name: Should be "nvidia,out-tmds-cfg"
+
+ - Child nodes represent tmds configurations. Several configurations can be prepared.
+
+ 1.B.i) NVIDIA HDMI TMDS configuration
+ This must be contained in nvidia,out-tmds-cfg parent node. This includes tmds configuration.
+
+ Required properties:
+ - name: Can be arbitrary, but each sibling node should have unique name.
+ - pclk: pixel clk required in tmds table for each mode.
+ - pll0: See HDMI_NV_PDISP_SOR_PLL0_0 in Tegra TRM.
+ - pll1: See HDMI_NV_PDISP_SOR_PLL1_0 in Tegra TRM.
+ - pe-current: Individual lane pre-emphasis current control (4bits per lane)
+   See HDMI_NV_PDISP_PE_CURRENT_0 in Tegra TRM.
+ - drive-current: TMDS per-lane I/O current control.
+   See HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_0 in Tegra TRM.
+ - peak-current: New pad controls for 28nm macro TMDS_X4_HP 8 bits per lane.
+   See HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_0 in Tegra TRM.
+
 Example
 	host1x {
 		hdmi {
diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt b/Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt
index f93d77c21edf..96b5d2242450 100644
--- a/Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt
+++ b/Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt
@@ -66,29 +66,6 @@ NVIDIA Tegra124 Display Controller
    For hdmi out-type case, depth selection is only valid for hdmi fb console mode,
    otherwise, BASE_COLOR_SIZE888 is chosen as a default.
 
- 1.B.i) NVIDIA Display Controller TMDS configurations
- This must be contained in dc-default-out parent node. This includes tmds configurations.
-
- Required properties:
- - name: Should be "nvidia,out-tmds-cfg"
-
- - Child nodes represent tmds configurations. Several configurations can be prepared.
-
- 1.B.i.x) NVIDIA Display Controller TMDS configuration
- This must be contained in nvidia,out-tmds-cfg parent node. This includes tmds configuration.
-
- Required properties:
- - name: Can be arbitrary, but each sibling node should have unique name.
- - pclk: pixel clk required in tmds table for each mode.
- - pll0: See HDMI_NV_PDISP_SOR_PLL0_0 in Tegra TRM.
- - pll1: See HDMI_NV_PDISP_SOR_PLL1_0 in Tegra TRM.
- - pe-current: Individual lane pre-emphasis current control (4bits per lane)
-   See HDMI_NV_PDISP_PE_CURRENT_0 in Tegra TRM.
- - drive-current: TMDS per-lane I/O current control.
-   See HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_0 in Tegra TRM.
- - peak-current: New pad controls for 28nm macro TMDS_X4_HP 8 bits per lane.
-   See HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_0 in Tegra TRM.
-
 1.C) NVIDIA Display Controller framebuffer data
  This must be contained in dc parent node. This is required framebuffer data.
 
diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt b/Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt
index 4e7ee113c09a..b038efd5eee7 100644
--- a/Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt
+++ b/Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt
@@ -23,6 +23,29 @@ NVIDIA TEGRA124 High Definition Multimedia Interface
  - regulator names for supply voltage, PLL and hdmi 5V source should be avdd_hdmi, avdd_hdmi_pll,
    vdd_hdmi_5v0, respectively.
 
+ 1.B) NVIDIA HDMI TMDS configurations
+ This must be contained in hdmi parent node. This includes tmds configurations.
+
+ Required properties:
+ - name: Should be "nvidia,out-tmds-cfg"
+
+ - Child nodes represent tmds configurations. Several configurations can be prepared.
+
+ 1.B.i) NVIDIA HDMI TMDS configuration
+ This must be contained in nvidia,out-tmds-cfg parent node. This includes tmds configuration.
+
+ Required properties:
+ - name: Can be arbitrary, but each sibling node should have unique name.
+ - pclk: pixel clk required in tmds table for each mode.
+ - pll0: See HDMI_NV_PDISP_SOR_PLL0_0 in Tegra TRM.
+ - pll1: See HDMI_NV_PDISP_SOR_PLL1_0 in Tegra TRM.
+ - pe-current: Individual lane pre-emphasis current control (4bits per lane)
+   See HDMI_NV_PDISP_PE_CURRENT_0 in Tegra TRM.
+ - drive-current: TMDS per-lane I/O current control.
+   See HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_0 in Tegra TRM.
+ - peak-current: New pad controls for 28nm macro TMDS_X4_HP 8 bits per lane.
+   See HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_0 in Tegra TRM.
+
 Example
 	host1x {
 		hdmi {