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author | Stefan Agner <stefan.agner@toradex.com> | 2015-08-04 18:19:42 +0200 |
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committer | Stefan Agner <stefan.agner@toradex.com> | 2015-08-04 18:19:42 +0200 |
commit | 8f4fb1c1d6e4c7804d6d3db69986642199d801e9 (patch) | |
tree | e4f2b00217d04a6c2c7b14ca3fada76e8e10c1e6 /Documentation | |
parent | 49662c2e2fcede96ed0a55c7838265e3ed781a52 (diff) | |
parent | aaa847711ebdb33592f7e4136be2eeac14b83137 (diff) |
Merge branch 'vf610-suspend-4.1-lpstop2' into toradex_vf_4.1-next
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/arm/freescale/fsl,vf610-ddrmc.txt | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-ddrmc.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-ddrmc.txt new file mode 100644 index 000000000000..56a71d6bb423 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-ddrmc.txt @@ -0,0 +1,23 @@ +Freescale Vybrid LPDDR2/DDR3 SDRAM Memory Controller + +The memory controller supports high performance applications for 16-bit or +8-bit DDR2, or LPDDR SDRAM memories. + +Required properties: +- compatible: "fsl,vf610-ddrmc" +- reg: the register range of the DDRMC registers +- clocks: DDRMC main clock to clock memory and access registers. +- clock-names: Must contain "ddrc", matching entry in the clocks property. +- fsl,has-cke-reset-pulls: + States whether pull-down/up are populated on DDR CKE/RESET + signals to allow using DDR self-refresh modes (see Vybrid + Hardware Development Guide for details). + +Example: + ddrmc: ddrmc@400ae000 { + compatible = "fsl,vf610-ddrmc"; + reg = <0x400ae000 0x1000>; + clocks = <&clks VF610_CLK_DDRMC>; + clock-names = "ddrc"; + fsl,has-cke-reset-pulls; + } |