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authorRobby Cai <R63905@freescale.com>2014-03-11 18:41:45 +0800
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 08:57:58 -0500
commit0bbdbb89b92a70997d3a33075bc34e948eea8d9d (patch)
tree5730cd456d1b56682a1fd88fb64e6700a5769974 /Documentation
parentb14266fa5337375ce4b4008e8eb8315afda5227b (diff)
ENGR00302869-1 ARM: dts: imx6qdl: add cfg_clk for MIPI CSI2
MIPI CSI2 depends on this clock to work. This patch also updates the binding document. Signed-off-by: Robby Cai <R63905@freescale.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt4
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt b/Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt
index 4b502809fc2d..d10f23721f34 100644
--- a/Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt
+++ b/Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt
@@ -27,8 +27,8 @@ for SOC imx6qdl.dtsi:
compatible = "fsl,imx6q-mipi-csi2";
reg = <0x021dc000 0x4000>;
interrupts = <0 100 0x04>, <0 101 0x04>;
- clocks = <&clks 138>, <&clks 53>;
- clock-names = "dphy_clk", "pixel_clk";
+ clocks = <&clks 138>, <&clks 53>, <&clks 204>;
+ clock-names = "dphy_clk", "pixel_clk", "cfg_clk";
status = "disabled";
};