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authorLiu Ying <Ying.Liu@freescale.com>2013-08-20 14:37:47 +0800
committerJason Liu <r64343@freescale.com>2013-08-23 07:30:32 +0800
commit624dda6238a81d1f5658bd2406dcd45ce040e70d (patch)
tree7fefcc7e1166a1f8006b36ffd8cb7f1cac45ec26 /Documentation
parent8e5f454697f5a129c0d4998030bc3819d0cea6fa (diff)
ENGR00274172-1 ARM: imx6q: refactor some ldb related clocks
The ldb_di[0|1]_ipu_div dividers may divide their parent clock frequencies by either 3.5 or 7. The non-integral dividers cannot be dealt with the common clock framework, so they cannot be registered as common clock dividers. So this patch adds a fixed factor clock of 1/7 and introduces ldb_di[0|1]_div_sel multiplexers so that the fixed factor clocks of 1/3.5 and 1/7 can be set to be the parents of ldb_di[0|1]_div_sel multiplexers. The ldb_di[0|1]_podf dividers are no longer used then. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/clock/imx6q-clock.txt6
1 files changed, 4 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 74535417dc33..f51a2e77f9b3 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -89,8 +89,6 @@ clocks and IDs.
gpu3d_shader 74
ipu1_podf 75
ipu2_podf 76
- ldb_di0_podf 77
- ldb_di1_podf 78
ipu1_di0_pre 79
ipu1_di1_pre 80
ipu2_di0_pre 81
@@ -217,6 +215,10 @@ clocks and IDs.
vdoa 202
gpt_3m 203
video_27m 204
+ ldb_di0_div_7 205
+ ldb_di1_div_7 206
+ ldb_di0_div_sel 207
+ ldb_di1_div_sel 208
Examples: