diff options
| author | Shawn Guo <shawn.guo@freescale.com> | 2014-06-05 15:36:30 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-08-27 18:29:07 -0500 |
| commit | 88f0720f2d1d15dd5bddb084f34ab601fdc77911 (patch) | |
| tree | 0734299bec3031621034cabe4dd01ab4617bbe71 /Documentation | |
| parent | 506ebb1671bf13734101f77b2b6460b5793598e0 (diff) | |
ENGR00318063-8: ARM: imx6q: hide buggy ldb_di_sel from clk API
The clk_set_parent() on the buggy mux ldb_di0_sel and ldb_di1_sel can
possibly lock up the downstream divider and result in no clock output.
Let's hard-code the parent to be pll2_pfd0_352m at boot time, and hide
these two buggy muxes from clk API. Then no clk_set_parent() can be
called on these muxes to switch parent clock at run-time.
Kernel parameter 'ldb_di_clk_sel' is created to select parent of
ldb_di_clk among the following clocks at boot time.
'pll5_video_div'
'pll2_pfd0_352m'
'pll2_pfd2_396m'
'mmdc_ch1_axi'
'pll3_usb_otg'
Example format: ldb_di_clk_sel=pll5_video_div
If the kernel parameter is absent or invalid, pll2_pfd0_352m will be
selected by default.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/imx6q-clock.txt | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt index 300946718ae7..845cc69bc9b7 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt @@ -45,8 +45,6 @@ clocks and IDs. gpu3d_shader_sel 30 ipu1_sel 31 ipu2_sel 32 - ldb_di0_sel 33 - ldb_di1_sel 34 ipu1_di0_pre_sel 35 ipu1_di1_pre_sel 36 ipu2_di0_pre_sel 37 |