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authorLiu Ying <victor.liu@nxp.com>2016-12-05 13:38:22 +0800
committerJason Liu <jason.hui.liu@nxp.com>2019-02-12 10:26:52 +0800
commit4294d1c777c4e33549ad59a5835d08094ee9f7b6 (patch)
treee489a0504edb9ade803ca87a30166bd44d025b90 /Documentation
parent3538c60c4ca39030c8abe56132f044ff74eadccf (diff)
MLK-15001-10 gpu: Add dpu base driver
DPU is the display processing unit embedded in i.MX8qm and i.MX8qxp. It was originally designed by Fujitsu. The first revision has capture controller, display controller and blit engine. The second revision is a lite one and has display controller and blit engine. This patch adds a base driver for DPU, which provides a thin register wrapper, interrurpt support and client platform device register for the upper layer to use. Currently, the driver only supports the display controller at the pixel processing level and only the fetchdecodes are supported/tested as the fetch units. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt70
1 files changed, 70 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
index f79854783c2c..9fccfd4b40a8 100644
--- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
+++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
@@ -108,6 +108,76 @@ prg@21cc000 {
<&clks IMX6QDL_CLK_PRG0_AXI>;
clock-names = "ipg", "axi";
fsl,pres = <&pre1>, <&pre2>, <&pre3>;
+
+Freescale i.MX DPU
+====================
+
+Required properties:
+- compatible: Should be "fsl,<chip>-dpu"
+- reg: should be register base and length as documented in the
+ datasheet
+- intsteer: phandle pointing to interrupt steer.
+- interrupts, interrupt-names: Should contain interrupts and names as
+ documented in the datasheet.
+- clocks, clock-names: phandles to the DPU clocks described in
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+ The following clocks are expected on i.MX8qm and i.MX8qxp:
+ "pll0" - PLL clock for display interface 0
+ "pll1" - PLL clock for display interface 1
+ "disp0" - pixel clock for display interface 0
+ "disp1" - pixel clock for display interface 1
+ The needed clock numbers for each are documented in
+ Documentation/devicetree/bindings/clock/imx8qm-clock.txt, and in
+ Documentation/devicetree/bindings/clock/imx8qxp-clock.txt.
+- power-domains: phandle pointing to power domain.
+Optional properties:
+- port@[0-1]: Port nodes with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+ ports 0 and 1 should correspond to display interface 0 and
+ display interface 1, respectively.
+
+example:
+
+dpu: dpu@56180000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qm-dpu";
+ reg = <0x0 0x56180000 0x0 0x40000>;
+ intsteer = <&dpu1_intsteer>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_common",
+ "irq_stream0a",
+ "irq_stream0b",
+ "irq_stream1a",
+ "irq_stream1b",
+ "irq_reserved0",
+ "irq_reserved1",
+ "irq_blit";
+ clocks = <&clk IMX8QM_DC0_PLL0_CLK>,
+ <&clk IMX8QM_DC0_PLL1_CLK>,
+ <&clk IMX8QM_DC0_DISP0_CLK>,
+ <&clk IMX8QM_DC0_DISP1_CLK>;
+ clock-names = "pll0", "pll1", "disp0", "disp1";
+ power-domains = <&pd_dc0>;
+
+ dpu1_disp1: port@1 {
+ reg = <1>;
+
+ dpu1_disp1_lvds0: lvds0-endpoint {
+ remote-endpoint = <&ldb1_lvds0>;
+ };
+
+ dpu1_disp1_lvds1: lvds1-endpoint {
+ remote-endpoint = <&ldb1_lvds1>;
+ };
+ };
};
Parallel display support