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| author | Lucas Stach <l.stach@pengutronix.de> | 2014-07-23 19:52:38 +0200 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-01-15 21:18:46 -0600 |
| commit | d5c89dc7f65b106a823a29261bac9b93684ca5ba (patch) | |
| tree | c431cb44b799168f6cbdb0204d68958e01806ad5 /Documentation | |
| parent | 369baae0002ebd89715e45dc35f3a98178b49e10 (diff) | |
PCI: designware: Parse bus-range property from devicetree
This allows to explicitly specify the covered bus numbers in the
devicetree, which will come in handy once we see a SoC with more than one
PCIe host controller instance.
Previously the driver relied on the behavior of pci_scan_root_bus() to fill
in a range of 0x00-0xff if no valid range was found. We fall back to the
same range if no valid DT entry was found to keep backwards compatibility,
but now do it explicitly.
[bhelgaas: use %pR in error message to avoid duplication]
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
(cherry picked from commit 4f2ebe00597c44f7dc6f88a052a2981ddcf6a0b6)
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/designware-pcie.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index ed0d9b9fff2b..9f4faa8e8d00 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -23,3 +23,6 @@ Required properties: Optional properties: - reset-gpio: gpio pin number of power good signal +- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to + specify this property, to keep backwards compatibility a range of 0x00-0xff + is assumed if not present) |