diff options
| author | Alex Frid <afrid@nvidia.com> | 2014-02-21 23:50:05 -0800 |
|---|---|---|
| committer | Yu-Huan Hsu <yhsu@nvidia.com> | 2014-02-24 11:50:11 -0800 |
| commit | 51c6be67441c4f184cb74181c03956d2be3e930e (patch) | |
| tree | b63c6b98cad0c1974ef8a17fa52fc1147220248b /Documentation | |
| parent | ada321f30039993c2ad9fe2c90e029bcbe130afc (diff) | |
ARM: tegra: Add Tegra13 DFLL binding compatibility
Added Tegra DFLL binding compatibility with T132 SoC.
Bug 1442709
Change-Id: Ib15b9a73e634d4de97d1a17079c5637b27d3b86f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/373259
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt index 2188203dc2dc..09ee36938007 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt @@ -2,12 +2,15 @@ NVIDIA Tegra DFLL clock source data in the SoC DTS file: Required properties: - compatible : Must be one of the following + "nvidia,tegra132-dfll" "nvidia,tegra124-dfll" "nvidia,tegra148-dfll" "nvidia,tegra114-dfll" - reg : Must contain the starting physical address and length for the DFLL's MMIO register space including the DFLL-to-I2C controller interface and the - DFLL's I2C controller. + DFLL's I2C controller. If DFLL configuration and I2C register spaces are + not contiguous, 2 separate ranges should be specified with configuration + range as the first one. - out-clock-name : Must contain a "dfll_cpu" string, name of the DFLL output clock. @@ -15,7 +18,7 @@ Optional properties: - status : device availability -- managed by the DT integration code. Should be set to "disabled" in the SoC DTS file. -Example: +Examples: dfll@70110000 { compatible = "nvidia,tegra124-dfll"; @@ -24,6 +27,14 @@ dfll@70110000 { status = "disabled"; }; +dfll@70040084 { + compatible = "nvidia,tegra132-dfll"; + reg = <0x70040084 0x40>, + <0x70110000 0x400>; + out-clock-name="dfll_cpu"; + status = "disabled"; +}; + NVIDIA Tegra DFLL clock source data in the board DTS file @@ -132,7 +143,8 @@ cpu_dfll_pmic_integration { DFLL PWM PMIC integration subnode in the board DTS file Required properties: -- compatible : Must be +- compatible : Must be one of the following + "nvidia,tegra132-dfll-pwm" "nvidia,tegra124-dfll-pwm" - pwm-data-gpio : DFLL PWM data GPIO. |