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authorDavid Daney <>2011-07-05 16:34:46 -0700
committerRalf Baechle <>2011-07-26 06:47:47 +0100
commitbf28607fbe529e20180080c4a0295b0a47834fde (patch)
tree101ca3c89186e1feb07ceb61ba91a9150d19218f /MAINTAINERS
parentf0daaaf5236297ea81ec7732cd0df5dbd84a5042 (diff)
MIPS: Close races in TLB modify handlers.
Page table entries are made invalid by writing a zero into the the PTE slot in a page table. This creates a race condition with the TLB modify handlers when they are updating the PTE. CPU0 CPU1 Test for _PAGE_PRESENT . set to not _PAGE_PRESENT (zero) Set to _PAGE_VALID So now the page not present value (zero) is suddenly valid and user space programs have access to physical page zero. We close the race by putting the test for _PAGE_PRESENT and setting of _PAGE_VALID into an atomic LL/SC section. This requires more registers than just K0 and K1 in the handlers, so we need to save some registers to a save area and then restore them when we are done. The save area is an array of cacheline aligned structures that should not suffer cache line bouncing as they are CPU private. [ Fix !defined(CONFIG_MIPS_PGD_C0_CONTEXT) build error.] Signed-off-by: David Daney <> To: Patchwork: Signed-off-by: Ralf Baechle <>
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