MLK-24171-3 phy: pcie: imx8mp: verify the pll sys ref clock source

Verify the PCIe PLL_SYS reference clock source on EVK board.
The external OSC clock is used as PCIe REF clock source in default.
- sequence should be the following one.
phy configuration--> CMN_RSTN--> wait for pll lock
- add the calibrate callback to fit the correct init sequence of phy

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit 9afaf7a465858970aee8858fb52067f2ef152c7f)

0 files changed, 0 insertions, 0 deletions