diff options
| author | Keerthy <j-keerthy@ti.com> | 2015-06-18 13:31:13 +0530 |
|---|---|---|
| committer | Tero Kristo <t-kristo@ti.com> | 2015-07-31 12:13:18 +0300 |
| commit | dff8a207815a605872dfc5bffc1bae1cad29d87c (patch) | |
| tree | 9a90aebd7e43f5c043fb933cfc60c6481afb6e2c /arch/arm/boot/dts/am4372.dtsi | |
| parent | 93c03a2c36d2bc70d42acdeef12d0ac156ffecda (diff) | |
ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk clock
cpsw needs the clock to be running at 50MHz in kernel. Hence setting
the default rate.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'arch/arm/boot/dts/am4372.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/am4372.dtsi | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index ade28c790f4b..8091af6a99c3 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -527,8 +527,11 @@ #address-cells = <1>; #size-cells = <1>; ti,hwmods = "cpgmac0"; - clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; - clock-names = "fck", "cpts"; + clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>, + <&dpll_clksel_mac_clk>; + clock-names = "fck", "cpts", "50mclk"; + assigned-clocks = <&dpll_clksel_mac_clk>; + assigned-clock-rates = <50000000>; status = "disabled"; cpdma_channels = <8>; ale_entries = <1024>; |