diff options
| author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2013-04-12 16:29:06 +0200 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2013-04-15 15:00:12 +0000 |
| commit | 1b2529d018b7f8e3faa0011a49116d4df9e44777 (patch) | |
| tree | 55a0a4e9bb1d0ff4e7fcf4b74caefc1446b712f1 /arch/arm/boot/dts/armada-xp-mv78460.dtsi | |
| parent | b757f17e9184b65428c48a281d82f9acb3e96f0e (diff) | |
ARM: dts: mvebu: fix cpus section indentation
Align the cpu node indentation with the rest of the file
[gc]: added a commit description
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/armada-xp-mv78460.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/armada-xp-mv78460.dtsi | 54 |
1 files changed, 27 insertions, 27 deletions
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 23a5ac4490a8..b9da5b8ae288 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -27,36 +27,36 @@ cpus { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - }; + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; + }; - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - }; + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; + }; - cpu@2 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <2>; - clocks = <&cpuclk 2>; - }; + cpu@2 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <2>; + clocks = <&cpuclk 2>; + }; - cpu@3 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <3>; - clocks = <&cpuclk 3>; - }; + cpu@3 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <3>; + clocks = <&cpuclk 3>; + }; }; soc { @@ -300,4 +300,4 @@ }; }; }; - }; +}; |