diff options
| author | Jon Mason <jon.mason@broadcom.com> | 2017-07-31 17:54:23 -0400 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2017-08-07 10:32:20 -0700 |
| commit | bbe526f55b60b76a22dfe43e7c8ffe18f5eb30a3 (patch) | |
| tree | 31d4c51c3dacaa5761f2139ca353dee0b53fa032 /arch/arm/boot/dts/bcm-nsp.dtsi | |
| parent | 2c5b8512c5b6812c7b4547f93028f938c3b033be (diff) | |
ARM: dts: NSP: Add USB3 and USB3 PHY to NSP
This uses the existing Northstar USB3 PHY driver to enable the USB3
ports on NSP.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/bcm-nsp.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/bcm-nsp.dtsi | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 9feb3689d191..dff66974feed 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -302,6 +302,16 @@ #size-cells = <0>; }; + xhci: usb@29000 { + compatible = "generic-xhci"; + reg = <0x29000 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy>; + phy-names = "usb3-phy"; + dma-coherent; + status = "disabled"; + }; + ehci0: usb@2a000 { compatible = "generic-ehci"; reg = <0x2a000 0x100>; @@ -469,6 +479,15 @@ phy-names = "sata-phy"; }; }; + + usb3_phy: usb3-phy@104000 { + compatible = "brcm,ns-bx-usb3-phy"; + reg = <0x104000 0x1000>, + <0x032000 0x1000>; + reg-names = "dmp", "ccb-mii"; + #phy-cells = <0>; + status = "disabled"; + }; }; pcie0: pcie@18012000 { |