diff options
| author | Jon Mason <jonmason@broadcom.com> | 2016-05-05 19:29:30 -0400 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2016-05-31 10:56:09 -0700 |
| commit | d71eb941208883404d44380807726afdc20ab98a (patch) | |
| tree | 0c21495f87c9c5a3bc5f9fd41ef5981d1776b37e /arch/arm/boot/dts/bcm-nsp.dtsi | |
| parent | 6585cb5a1341cbc5dfcf99a9b4ebda338b03657e (diff) | |
ARM: dts: NSP: Add MSI support on PCI
Add MSI support to the PCI driver of the Northstar Plus SoC. This uses
the existing pcie-iproc driver. So, all that is needed is device tree
entries in the DTS.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/bcm-nsp.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/bcm-nsp.dtsi | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index def9e783b5c6..a44bf29fc5b6 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -290,6 +290,18 @@ ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; status = "disabled"; + + msi-parent = <&msi0>; + msi0: msi@18012000 { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>, + <GIC_SPI 128 IRQ_TYPE_NONE>, + <GIC_SPI 129 IRQ_TYPE_NONE>, + <GIC_SPI 130 IRQ_TYPE_NONE>; + brcm,pcie-msi-inten; + }; }; pcie1: pcie@18013000 { @@ -314,6 +326,18 @@ ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; status = "disabled"; + + msi-parent = <&msi1>; + msi1: msi@18013000 { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 133 IRQ_TYPE_NONE>, + <GIC_SPI 134 IRQ_TYPE_NONE>, + <GIC_SPI 135 IRQ_TYPE_NONE>, + <GIC_SPI 136 IRQ_TYPE_NONE>; + brcm,pcie-msi-inten; + }; }; pcie2: pcie@18014000 { @@ -338,5 +362,17 @@ ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; status = "disabled"; + + msi-parent = <&msi2>; + msi2: msi@18014000 { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>, + <GIC_SPI 140 IRQ_TYPE_NONE>, + <GIC_SPI 141 IRQ_TYPE_NONE>, + <GIC_SPI 142 IRQ_TYPE_NONE>; + brcm,pcie-msi-inten; + }; }; }; |