diff options
| author | Roger Quadros <rogerq@ti.com> | 2016-03-03 13:28:20 +0200 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2016-04-12 14:32:02 -0700 |
| commit | 91d075c7cf2cf621142c0a69f2acc690b81cb8a2 (patch) | |
| tree | 7a76ea05943023f22d3927f54b62cdafd496196d /arch/arm/boot/dts/dra7-evm.dts | |
| parent | 8695add6c3ac272677cd6e4414a4b3ed26f8a1f7 (diff) | |
ARM: dts: dra7-evm: Fix comment about NAND configuration
The switch configuration for NAND is actually the other way round.
Also mention ON/OFF states as that is more natural to understand
(without the help of schematics) when compared to HIGH/LOW.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7-evm.dts')
| -rw-r--r-- | arch/arm/boot/dts/dra7-evm.dts | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 6e61cfa12326..05c135d84374 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -256,8 +256,9 @@ nand_flash_x16: nand_flash_x16 { /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch * So NAND flash requires following switch settings: - * SW5.9 (GPMC_WPN) = LOW - * SW5.1 (NAND_BOOTn) = HIGH */ + * SW5.1 (NAND_BOOTn) = ON (LOW) + * SW5.9 (GPMC_WPN) = OFF (HIGH) + */ pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ |