diff options
| author | Kishon Vijay Abraham I <kishon@ti.com> | 2014-07-14 16:12:22 +0530 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2014-07-15 00:16:14 -0700 |
| commit | 692df0ef5abb7d8b36d70762134b842b70a55c31 (patch) | |
| tree | 3dd6bdbec95b946cc64d796c6e971f9c8e528f9f /arch/arm/boot/dts/dra7.dtsi | |
| parent | d1ff66b52dbe6ac7c13c77767759d1ac84f5da9d (diff) | |
ARM: dts: dra7: Add dt data for PCIe PHY
Added dt data for PCIe PHY as a child node of ocp2scp3.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt.
26.3.3 PCIe Shared PHY Subsystem Integration in vE of DRA7xx ES1.0
describes the PCIe PHY subsystem-related components integrated in the device.
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/dra7.dtsi | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index e4999e4b7b65..cbaf47db2b6e 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -816,6 +816,47 @@ clock-names = "sysclk"; #phy-cells = <0>; }; + + pcie1_phy: pciephy@4a094000 { + compatible = "ti,phy-pipe3-pcie"; + reg = <0x4a094000 0x80>, /* phy_rx */ + <0x4a094400 0x64>; /* phy_tx */ + reg-names = "phy_rx", "phy_tx"; + ctrl-module = <&omap_control_pcie1phy>; + clocks = <&dpll_pcie_ref_ck>, + <&dpll_pcie_ref_m2ldo_ck>, + <&optfclk_pciephy1_32khz>, + <&optfclk_pciephy1_clk>, + <&optfclk_pciephy1_div_clk>, + <&optfclk_pciephy_div>; + clock-names = "dpll_ref", "dpll_ref_m2", + "wkupclk", "refclk", + "div-clk", "phy-div"; + #phy-cells = <0>; + id = <1>; + ti,hwmods = "pcie1-phy"; + }; + + pcie2_phy: pciephy@4a095000 { + compatible = "ti,phy-pipe3-pcie"; + reg = <0x4a095000 0x80>, /* phy_rx */ + <0x4a095400 0x64>; /* phy_tx */ + reg-names = "phy_rx", "phy_tx"; + ctrl-module = <&omap_control_pcie2phy>; + clocks = <&dpll_pcie_ref_ck>, + <&dpll_pcie_ref_m2ldo_ck>, + <&optfclk_pciephy2_32khz>, + <&optfclk_pciephy2_clk>, + <&optfclk_pciephy2_div_clk>, + <&optfclk_pciephy_div>; + clock-names = "dpll_ref", "dpll_ref_m2", + "wkupclk", "refclk", + "div-clk", "phy-div"; + #phy-cells = <0>; + ti,hwmods = "pcie2-phy"; + id = <2>; + status = "disabled"; + }; }; sata: sata@4a141100 { |