diff options
| author | Krzysztof Kozlowski <krzk@kernel.org> | 2016-09-16 21:42:49 +0200 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2016-11-03 22:44:54 +0200 |
| commit | 6abdf8d135b77693e6f3f4ad8212bcbc6434eb2b (patch) | |
| tree | d417562bd63ad6a4b08a56fb18056251b51a8043 /arch/arm/boot/dts/exynos5410.dtsi | |
| parent | 27e64b27b688cae59fdcf339a90b29f6d14809d5 (diff) | |
ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5410/exynos542x
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Diffstat (limited to 'arch/arm/boot/dts/exynos5410.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/exynos5410.dtsi | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 137f48464f8b..dae5715b41b9 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -85,7 +85,7 @@ tmu_cpu0: tmu@10060000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10060000 0x100>; - interrupts = <GIC_SPI 65 0>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -94,7 +94,7 @@ tmu_cpu1: tmu@10064000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10064000 0x100>; - interrupts = <GIC_SPI 183 0>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -103,7 +103,7 @@ tmu_cpu2: tmu@10068000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10068000 0x100>; - interrupts = <GIC_SPI 184 0>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -112,7 +112,7 @@ tmu_cpu3: tmu@1006c000 { compatible = "samsung,exynos5420-tmu"; reg = <0x1006c000 0x100>; - interrupts = <GIC_SPI 185 0>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -121,7 +121,7 @@ mmc_0: mmc@12200000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12200000 0x1000>; - interrupts = <0 75 0>; + interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; @@ -133,7 +133,7 @@ mmc_1: mmc@12210000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12210000 0x1000>; - interrupts = <0 76 0>; + interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; @@ -145,7 +145,7 @@ mmc_2: mmc@12220000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12220000 0x1000>; - interrupts = <0 77 0>; + interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; @@ -157,31 +157,31 @@ pinctrl_0: pinctrl@13400000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x13400000 0x1000>; - interrupts = <0 45 0>; + interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 32 0>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; }; }; pinctrl_1: pinctrl@14000000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x14000000 0x1000>; - interrupts = <0 46 0>; + interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_2: pinctrl@10d10000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x10d10000 0x1000>; - interrupts = <0 50 0>; + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_3: pinctrl@03860000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x03860000 0x1000>; - interrupts = <0 47 0>; + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -329,7 +329,7 @@ }; &usbdrd_dwc3_1 { - interrupts = <GIC_SPI 200 0>; + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; }; &usbdrd_phy1 { |