diff options
| author | Sandor Yu <R01008@freescale.com> | 2015-09-21 17:34:34 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@nxp.com> | 2016-01-14 11:01:36 -0600 |
| commit | c15d2cd300e1ef5e5be369f7308090112fbfc367 (patch) | |
| tree | af31cecc032c32a29ea76c77105e090712c92508 /arch/arm/boot/dts/imx6dl.dtsi | |
| parent | 9bd019f58541793e9e291bd464eb5e9b673f41de (diff) | |
MLK-11508-5: dts: Add imx v4l2 capture driver
Add imx v4l2 capture driver.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6dl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6dl.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 69cee0eaac7e..781f86d31252 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -91,6 +91,12 @@ compatible = "fsl,imx6dl-iomuxc"; }; + dcic2: dcic@020e8000 { + clocks = <&clks IMX6QDL_CLK_DCIC1 >, + <&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/ + clock-names = "dcic", "disp-axi"; + }; + pxp: pxp@020f0000 { reg = <0x020f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; @@ -108,6 +114,16 @@ }; aips2: aips-bus@02100000 { + mipi_dsi: mipi@021e0000 { + compatible = "fsl,imx6dl-mipi-dsi"; + reg = <0x021e0000 0x4000>; + interrupts = <0 102 0x04>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; + clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; + status = "disabled"; + }; + i2c4: i2c@021f8000 { #address-cells = <1>; #size-cells = <0>; |