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authorPhilipp Zabel <p.zabel@pengutronix.de>2017-06-12 11:23:54 -0700
committerShawn Guo <shawnguo@kernel.org>2017-06-14 23:06:02 +0800
commitbc97e88ecd360a730b0f9c96f285b680be496e06 (patch)
tree78c0add3d9a362af8107a277c54dc589cc761b59 /arch/arm/boot/dts/imx6q.dtsi
parentcc20028f68e760d6958e892aba1f9bafbce63e22 (diff)
ARM: dts: imx6qdl: add multiplexer controls
The IOMUXC General Purpose Register space contains various bitfields that control video bus multiplexers. Describe them using a mmio-mux node. The placement of the IPU CSI video mux controls differs between i.MX6D/Q and i.MX6S/DL. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index dd33849335b2..1a14ae2ce6d8 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -332,6 +332,16 @@
};
};
+&mux {
+ mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
+ <0x04 0x00100000>, /* MIPI_IPU2_MUX */
+ <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
+ <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
+ <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
+ <0x28 0x00000003>, /* DCIC1_MUX_CTL */
+ <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
+};
+
&vpu {
compatible = "fsl,imx6q-vpu", "cnm,coda960";
};