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authorFabio Estevam <fabio.estevam@freescale.com>2013-09-17 13:46:23 -0300
committerShawn Guo <shawn.guo@linaro.org>2013-09-26 13:01:35 +0800
commite367817a0ae7065a60815933df0980e53b14c517 (patch)
treec14b26e369354f472af175fd31a98e19e541f4fd /arch/arm/boot/dts/imx6qdl-sabresd.dtsi
parent93e2ca0285da7eb9fe800663bbaa23cc74e0372b (diff)
ARM: dts: imx6qdl-sabresd: SDHC ports are 8 bit-wide
On imx6qdl-sabresd the SDHC2 and SDHC3 are 8 bit-wide, so pass the bus-width property to reflect that. Otherwise the mmc driver will operate with the default bus-width value of 4. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabresd.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 39eafc222a2e..64e454bcc4a3 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -229,6 +229,7 @@
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_1>;
+ bus-width = <8>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
status = "okay";
@@ -237,6 +238,7 @@
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
+ bus-width = <8>;
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
status = "okay";