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authorPeter Chen <peter.chen@freescale.com>2015-02-02 16:29:00 +0800
committerLi Jun <jun.li@nxp.com>2016-01-15 12:51:40 +0800
commit3df5fc1d21d25ff4c94a44f9bc935271da4021f3 (patch)
tree89c2165b368eece1d3372c7573fdd1bb5175ba37 /arch/arm/boot/dts/imx6qdl.dtsi
parent2bcd16a9e250b21f8e7ad8cbf945266213036cde (diff)
MLK-10196-1 ARM: imx6: change anatop 3p0 property
- Delete regulator-always-on for 3p0 since it needs to enable/disable on the fly. - Add "anatop-enable-bit" property as the offset of enable bit for 3p0, 1p1, and 2p5. - USB PHY refers "reg_3p0" phandle at its node. Signed-off-by: Peter Chen <peter.chen@freescale.com> (cherry picked from commit c2c2cbc46fda3e8ea798d270a3410f351af9d1ca)
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi12
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index e385191f9a3b..4224d547aa1c 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -655,20 +655,21 @@
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
+ anatop-enable-bit = <0>;
};
- regulator-3p0@120 {
+ reg_3p0: regulator-3p0@120 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <3150000>;
- regulator-always-on;
+ regulator-min-microvolt = <2625000>;
+ regulator-max-microvolt = <3400000>;
anatop-reg-offset = <0x120>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
+ anatop-enable-bit = <0>;
};
regulator-2p5@130 {
@@ -683,6 +684,7 @@
anatop-min-bit-val = <0>;
anatop-min-voltage = <2000000>;
anatop-max-voltage = <2750000>;
+ anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore@140 {
@@ -753,6 +755,7 @@
reg = <0x020c9000 0x1000>;
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_USBPHY1>;
+ phy-3p0-supply = <&reg_3p0>;
fsl,anatop = <&anatop>;
};
@@ -761,6 +764,7 @@
reg = <0x020ca000 0x1000>;
interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_USBPHY2>;
+ phy-3p0-supply = <&reg_3p0>;
fsl,anatop = <&anatop>;
};