summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/imx6qdl.dtsi
diff options
context:
space:
mode:
authorPhilipp Zabel <p.zabel@pengutronix.de>2015-02-23 18:40:13 +0100
committerShawn Guo <shawn.guo@linaro.org>2015-03-30 16:43:32 +0800
commit729c88812fa0fdb5188b23b6da425619741faf6d (patch)
treee26678d16945aebe6d938886a651fbd64c09ffd9 /arch/arm/boot/dts/imx6qdl.dtsi
parent3ec481ed05a5d4b567d5063483a0fdca5b81a6ae (diff)
ARM: dts: imx6qdl: Add power-domain information to gpc node
The PGC that is part of GPC controls isolation and power sequencing of the power domains. The PU power domain will be handled by the generic pm domain framework. It needs a phandle to the PU regulator to turn off power when the domain is disabled, and a list of phandles to all clocks that must be enabled during powerup for reset propagation. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 3a2d05432d70..76f4997d86fc 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -700,6 +700,14 @@
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
<0 90 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
+ pu-supply = <&reg_pu>;
+ clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+ <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+ <&clks IMX6QDL_CLK_GPU2D_CORE>,
+ <&clks IMX6QDL_CLK_GPU2D_AXI>,
+ <&clks IMX6QDL_CLK_OPENVG_AXI>,
+ <&clks IMX6QDL_CLK_VPU_AXI>;
+ #power-domain-cells = <1>;
};
gpr: iomuxc-gpr@020e0000 {