diff options
| author | Bai Ping <b51503@freescale.com> | 2015-09-06 22:03:16 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:23:09 +0800 |
| commit | f0d68c08dc27ecc3ac43a11ed19c48cbd57b116f (patch) | |
| tree | 3caf0436a14ba839f7b57fef40c36d136ac2c51b /arch/arm/boot/dts/imx6sl.dtsi | |
| parent | 16986284edbfbd296116829c5ce1ba376ddd4268 (diff) | |
MLK-11495-01 ARM: dts: imx: add busfreq device node for imx6sl
Add busfreq device node for imx6sl.
Signed-off-by: Bai Ping <b51503@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6sl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6sl.dtsi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index d9acd0a4c718..010293e2211f 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -115,6 +115,27 @@ interrupt-parent = <&gpc>; ranges; + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6SL_CLK_PLL2_BUS>, <&clks IMX6SL_CLK_PLL2_PFD2>, + <&clks IMX6SL_CLK_PLL2_198M>, <&clks IMX6SL_CLK_ARM>, + <&clks IMX6SL_CLK_PLL3_USB_OTG>, <&clks IMX6SL_CLK_PERIPH>, + <&clks IMX6SL_CLK_PRE_PERIPH_SEL>, <&clks IMX6SL_CLK_PERIPH_CLK2_PODF>, + <&clks IMX6SL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SL_CLK_OSC>, + <&clks IMX6SL_CLK_PLL1_SYS>, <&clks IMX6SL_CLK_PERIPH2>, + <&clks IMX6SL_CLK_AHB>, <&clks IMX6SL_CLK_OCRAM_PODF>, + <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>, + <&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2_PODF>, + <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_PLL2_BYPASS_SRC>, <&clks IMX6SL_PLL2_BYPASS>, + <&clks IMX6SL_CLK_PLL2>, <&clks IMX6SL_CLK_PLL1>, <&clks IMX6SL_PLL1_BYPASS>, + <&clks IMX6SL_PLL1_BYPASS_SRC>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", + "ocram", "pll1_sw", "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "pll2_bypass_src", + "pll2_bypass", "pll2", "pll1", "pll1_bypass", "pll1_bypass_src"; + fsl,max_ddr_freq = <400000000>; + }; + ocrams: sram@00900000 { compatible = "fsl,lpm-sram"; reg = <0x00900000 0x4000>; |