diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2019-05-04 20:47:05 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:26 +0800 |
| commit | cd8bc8edd7fbdea60826347a7005ac8ee7831218 (patch) | |
| tree | b5e113237f88dca4d4feb62c4a9fcca86d06de2e /arch/arm/boot/dts/imx6sl.dtsi | |
| parent | b3db7efdc5bc616785adeac241fc094ea9348ef3 (diff) | |
arm: dts: imx: update the clocks of cpu node
Update the clocks of cpu to match with the
cpufreq driver.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6sl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6sl.dtsi | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 200b5254c2b0..3aa014573dab 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -66,11 +66,17 @@ >; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; - clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, - <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, - <&clks IMX6SL_CLK_PLL1_SYS>; + clocks = <&clks IMX6SL_CLK_ARM>, + <&clks IMX6SL_CLK_PLL2_PFD2>, + <&clks IMX6SL_CLK_STEP>, + <&clks IMX6SL_CLK_PLL1_SW>, + <&clks IMX6SL_CLK_PLL1_SYS>, + <&clks IMX6SL_CLK_PLL1>, + <&clks IMX6SL_PLL1_BYPASS>, + <&clks IMX6SL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", "pll1_bypass", + "pll1_bypass_src"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; |