diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2017-12-01 18:44:03 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-12-21 14:29:20 +0100 |
| commit | 8ef8ae51ec6c642895a710e7db663178c557302c (patch) | |
| tree | e62ef4e58fa1950998480d4e077f23d78beb5e9e /arch/arm/boot/dts/imx6ull-colibri.dtsi | |
| parent | 141418d4fc9b1895e94880152402f23995011cca (diff) | |
ARM: dts: imx6ull: improve clock accuracy for SD High Speed
The High Speed SD interface requires a clock of 50MHz. Using a
base clock of 198MHz allows for a more accurate clock than using
132MHz base clock.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6ull-colibri.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6ull-colibri.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 4ed695f39a25..25aad2654424 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -623,3 +623,8 @@ dr_mode = "host"; }; +&usdhc1 { + assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; |