diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2017-03-26 14:48:07 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-04-03 15:09:42 +0200 |
| commit | 2cefbe750a0d20c0d7f71978af38956d4cf47926 (patch) | |
| tree | 37cf435d09434e8e3d052867cf9f9f8e25d6bfa9 /arch/arm/boot/dts/imx7-colibri.dtsi | |
| parent | 9667ac21619a16bb0c280372fd4bb14be08d07f6 (diff) | |
ARM: dts: imx7-colibri: follow lpsr iomux pin name change
Commit 5fd79049c122bd0f7bd906f676d3b8d65765a280 added _LPSR to all iomux
pin names which are controlled by the lpsr iomux.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7-colibri.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7-colibri.dtsi | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index 1231815ed25f..49b3341f9f64 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -668,33 +668,33 @@ imx7d-colibri { pinctrl_gpio1: gpio1grp { fsl,pins = < - MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x14 /* SODIMM 135 */ - MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x14 /* SODIMM 22 */ + MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x14 /* SODIMM 135 */ + MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14 /* SODIMM 22 */ >; }; pinctrl_gpiokeys: gpiokeysgrp { fsl,pins = < - MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x19 + MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < - MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f - MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f + MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f + MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f >; }; pinctrl_cd_usdhc1: usdhc1-cd-grp { fsl,pins = < - MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */ + MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */ >; }; pinctrl_uart1_ctrl2: uart1-ctrlgrp2 { /* Additional DSR, RI */ fsl,pins = < - MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14 /* DSR */ - MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x14 /* RI */ + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* DSR */ + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* RI */ >; }; }; |