diff options
| author | Han Xu <b45815@freescale.com> | 2015-01-29 07:07:19 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@nxp.com> | 2016-01-14 11:02:37 -0600 |
| commit | 0dcfd6580e20dffcf24cb96136839a4f29128a47 (patch) | |
| tree | 80e69fe399970ccea312565ef6ec8025051feb9d /arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-qspi.dts | |
| parent | 4a5ff4255d073cd5dc174691e47a6c6c5461eef3 (diff) | |
MLK-10205-1 ARM: dts: Create new dts for QSPI on i.MX7D
create a new dts file for QSPI verification on i.MX7D
Signed-off-by: Han Xu <b45815@freescale.com>
(cherry picked and merge from commit 2888c54189b6126519cf4c05094891980f321917)
Diffstat (limited to 'arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-qspi.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-qspi.dts | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-qspi.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-qspi.dts new file mode 100644 index 000000000000..db0133b45ce6 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-qspi.dts @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-12x12-lpddr3-arm2.dts" + +/* disable epdc, conflict with qspi */ +&epdc { + status = "disabled"; +}; + +&iomuxc { + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x51 + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x51 + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x51 + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x51 + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x51 + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x51 + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x51 + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x51 + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x51 + >; + }; + }; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; |